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PDSP16488MA Datasheet(PDF) 1 Page - Mitel Networks Corporation |
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PDSP16488MA Datasheet(HTML) 1 Page - Mitel Networks Corporation |
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1 / 33 page  PDSP16488A Single Chip 2D Convolver with Integral Line Delays Advance Information Supersedes version in 1996 Media IC Handbook, HB4599-1.0 DS3713 - 6.4 December 1997 and the PDSP16488A MA data sheet, DS3742 The PDSP16488A is a fully integrated, application specific, image processing device. It performs a two dimensional convo- lution between the pixels within a video window and a set of stored coefficients. An internal multiplier accumulator array can be multi-cycled at double or quadruple the pixel clock rate. This then gives the window size options listed in Table 1. An internal 32kbit RAM can be configured to provide either four or eight line delays. The length of each delay can be programmed to the users requirement, up to a maximum of 1024 pixels per line. The line delays are arranged in two groups,which may be internally connected in series or may be configured to accept separate pixel inputs. This allows interlaced video or frame to frame operations to be supported. The 8-bit coefficients are also stored internally and can be downloaded from a host computer or from an EPROM. No additional logic is required to support the EPROM and a single device can support up to 16 convolvers. The PDSP16488A contains an expansion adder and delay network which allows several devices to be cascaded. Con- volvers with larger windows can then be fabricated as shown in Table 2. Intermediate 32-bit precision is provided to avoid any danger of overflow, but the final result will not normally occupy all bits. The PDSP16488A thus provides a gain control block in the output path, which allows the user to align the result to the most significant end of the 32-bit word. Table 2 PDSP16488As needed to implement typical window sizes Pixel size Width Window size Depth Maximum pixel rate (MHz) Line delays 8 8 8 16 16 4 8 8 4 8 4 4 8 4 4 20 20 10 20 10 4 1024 4 1024 8 512 4 512 4 512 Table 1 Single PDSP16488A configurations Max. pixel rate (MHz) Pixel size 3 3 5 5 7 7 9 9 11 11 15 15 23 23 No. of PDSP16488As for N N window size 10 10 20 20 40 40 8 16 8 16 8 16 1 1 1 1 1 2 1 2 2 4 4* - 1 2 2 4 4* - 4 - 6 - - - 4 - 6 - - - 4 - 8 - - - 9 - - - - - *Maximum rate is limited to 30MHz by line store expansion delays ORDERING INFORMATION Commercial (0°C to 70°C) PDSP16488A / C0 / AC (PGA) Industrial ( 40°C to 85°C) PDSP16488A / B0 / AC (PGA) PDSP16488A / B0 / GC (QFP) Military ( 55°C to 125°C) PDSP16488A / A0 / AC (PGA) PDSP16488A / A0 / GC (QFP) PDSP16488A / MA / ACBR (PGA) MIL-STD-883 Class B* PDSP16488A / MA / GCPR (QFP) MIL-STD-883 Class B* *See Notes following Static Electrical CharacteristicsTable Note: PDSP16488A devices are not guaranteed to cascade with PDSP16488 devices. Mitel Semiconductor do not recommend that PDSP16488A be mixed with PDSP16488 devices in a single equipment design. The PDSP16488A requires external pullup resistors in EPROM Mode (see Static Electrical Characteristics). FEATURES s The PDSP16488A is a replacement for the PDSP16488 (see Note below) s 8 or 16-bit Pixels with rates up to 40 MHz s Window Sizes up to 8 8 with a Single Device s Eight Internal Line Delays s Supports Interlace and Frame-to-Frame Operations s Coefficients Supplied from an EPROM or Remote Host s Expandable in both X and Y for Larger Windows s Gain Control and Pixel Output Manipulation s 84-pin PGA or 132-pin QFP Package Options Fig. 1 Typical stand-alone real time system PDSP16488A EPROM ADDR DATA POWER ON RESET DELAYED SYNC OUTPUT DATA RES DELOP CLK HRES BYPASS SYNC EXTRACT COMPOSITE DATA PIXEL CLOCK GEN ADC OPTIONAL FIELD DELAY IP7:0 L7:0 D15:0 SYNC ODD FIELD |
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