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PDSP1601MC Datasheet(PDF) 8 Page - Mitel Networks Corporation |
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PDSP1601MC Datasheet(HTML) 8 Page - Mitel Networks Corporation |
8 / 17 page PDSP1601/PDSP1601A 8 The Register Files There are two on-chip register files (ALU and Shifter), each containing two 16 bit registers and each supporting 8 instructions (see Table 4). The instructions for the ALU register file and the Barrel Shifter Register file are the same. The Inputs to the register files come from either the ALU or the Barrel Shifter, and are loaded into the Register files on the rising edge of CLK. The register file instructions are latched such that the instruction will not start executing until the rising edge of the CLK latches the instruction into the device. The register file instructions (see Table 4) allow input data to be loaded into either, neither or both of the registers. Data is loaded at the end of the cycle in which the instruction is executing. The register file instructions allow the output to be sourced from either of the two registers, the selected output will be valid during the cycle in which the instruction is executing. Operation Load Left Reg Output Right Reg Load Right Reg Output Left Reg Load Left Register, Output Left Reg Load Right Register, Output Right Reg Load Both Registers, Output Left Reg No Load Operation, Output Right Reg No Load Operation, Output Left Reg No Load Operation, Pass Barrel Shifter Result Operation Load Left Reg Output Right Reg Load Right Reg Output Left Reg Load Left Register, Output Left Reg Load Right Register, Output Right Reg Load Both Registers, Output Left Reg No Load Operation, Output Right Reg No Load Operation, Output Left Reg No Load Operation, Pass ALU Result Inst 0 1 2 3 4 5 6 7 RA2-RA0 000 001 010 011 100 101 110 111 Mnemonic LLRRR LRRLR LLRLR LRRRR LBRLR NOPRR NOPLR NOPPS ALU REGISTER INSTRUCTIONS Inst 0 1 2 3 4 5 6 7 RA2-RA0 000 001 010 011 100 101 110 111 Mnemonic LLRRR LRRLR LLRLR LRRRR LBRLR NOPRR NOPLR NOPPS SHIFTER REGISTER INSTRUCTIONS Table 4 ALU and shift register instructions mnemonics MNEMONICS LXXYY Load XX = Target, YY = Source of Output LBOXX Load Both Registers, XX = Source of Output NOPXX No Load Operation, XX = Source of Output |
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