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NWK914CG Datasheet(PDF) 6 Page - Mitel Networks Corporation

Part # NWK914CG
Description  PHY/PMD High Speed Copper Media Transceiver
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Manufacturer  MITEL [Mitel Networks Corporation]
Direct Link  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

NWK914CG Datasheet(HTML) 6 Page - Mitel Networks Corporation

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NWK914D
Pin Name
Pin Type
Pin Number
Pin Description
SYMBOL Interface
RXC
TTLOP
4
25MHz recovered receive clock. This is aligned with and used to clock
out the 5 bit parallel receive data to the PCS layer.
SDT
TTLOP
5
Signal detect output. This output is high when an input signal of sufficient
amplitude is detected on the RXI inputs.
TDAT4
TTLIP
40
The 100BASE-TX transmit input bit 4
TDAT3
TTLIP
41
The 100BASE-TX transmit input bit 3
TDAT2
TTLIP
42
The 100BASE-TX transmit input bit 2
TDAT1
TTLIP
43
The 100BASE-TX transmit input bit 1
TDAT0
TTLIP
44
The 100BASE-TX transmit input bit 0
TXC
TTLOP
47
25MHz transmit clock. This is aligned with and used to clock in the 5 bit parallel
100BASE-TX transmit data from the PCS layer.
RDAT0
TTLOP
48
The 100BASE-TX receive output bit 0
RDAT1
TTLOP
49
The 100BASE-TX receive output bit 1
RDAT2
TTLOP
50
The 100BASE-TX receive output bit 2
RDAT3
TTLOP
51
The 100BASE-TX receive output bit 3
RDAT4
TTLOP
52
The 100BASE-TX receive output bit 4
Network Interface
RXIP
analog input
15
+ Differential receive signal input from magnetics
RXIN
analog input
16
– Differential receive signal input from magnetics
TXON
analog output
22
– Differential transmit line driver outputs to magnetics
TXOP
analog output
23
+ Differential transmit line driver outputs to magnetics
10BASE-T Interface
10TXIN
analog input
19
The filtered 10BASE-T transmit input (–)
10TXIP
analog input
20
The filtered 10BASE-T transmit input (+)
Control Pins
N10/100
TTLIP
36
10/100 mode selection. A low selects the 10BASE-T mode and enables the
data on pins 10TXIP/N to be outut on the TXOP/N pins. A high selects the
100BASE-TX mode, enabling the 100Mb/s drivers.
EQSEL
3 level IP
18
Mode select input for equalizer. Normally this pin is left unconnected (floating) for
auto-eq. mode. High selects minimum equalization. Low selects full equalization.
LBEN
TTLIP
35
Loopback enable input. A high on this pin selects the loopback mode and low selects
normal operation.
TXOE
TTLIP
33
Transmit output enable. A high on this pin selects normal operation. A low on this
pin puts both of the TX drivers in tri-state mode.
TESTIP
test
37
Test pin. This pin must be left unconnected for proper operation.
TEST
test
38
Test pin. This pin must be left unconnected for proper operation.
N/C
2,3,7,8
No connection. This pin must be left unconnected for proper operation.
Component Connections
REFCLK
TTLIP
45
25MHz clock input. An external 25MHz oscillator is input to this pin.
TXREF
analog input
25
TXOP/N line driver current setting pin. Connects to TXGND through a resistor.
LFRB
analog
10
Differential loop filter pin for receive PLL (see fig.6)
LFRA
analog
11
Differential loop filter pin for receive PLL (see fig.6)
LFTB
analog
30
Differential loop filter pin for transmit clock PLL (see fig.6)
LFTA
analog
31
Differential loop filter pin for transmit clock PLL (see fig.6)
Power
TTLGND
Power
1,39
GND for TTL logic I/Os
RDLV
CC
Power
6
+5V supply to receive logic
RXPLLGND
Power
9
GND to receive PLL
RXPLLV
CC
Power
12
+5V supply to receive PLL
RXV
CC2
Power
13
+5V supply to adaptive equalizer and QFB circuits
RXGND
Power
14
GND to to adaptive equalizer and QFB circuits
RXV
CC1
Power
17
+5V supply to MLT-3 to NRZI converter
TXV
CC
Power
21
+5V supply to transmit line driver circuits
TXGND
Power
24
GND to transmit line driver circuits
RXV
CC
Power
26
+5V supply to on-chip bandgap reference
SUBGND
Power
27
Chip substrate GND connection
BGAPGND
Power
28
GND to on-chip bandgap reference
TXPLLGND
Power
29
GND to to transmit clock-multiplier PLL
TXPLLV
CC
Power
32
+5V supply to transmit clock-multiplier PLL
TDLV
CC
Power
34
+5V supply to transmit logic
TXLV
CC
Power
46
+5V supply to TTL logic I/Os
Table 1: Pin descriptions


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