Advance Information

MT9162

7-171

Figure 5 - SSI Synchronous Timing Diagram

† Timing is over recommended temperature range & recommended power supply voltages.

‡ Typical figures are at 25

Characteristics

Sym

Min

Max

Units

Test Conditions

1

Bit Cell Period

7812

3906

ns

ns

BCL=128 kHz

BCL=256 kHz

2

Frame Jitter

600

ns

3

Bit 1 Dout Delay from STB

going high

ns

4

Bit 2 Dout Delay from STB

going high

600+

600+

600 +

ns

5

Bit n Dout Delay from STB

going high

600 +

(n-1) x

600 +

(n-1) x

600 +

(n-1) x

ns

n=3 to 8

6

Bit 1 Data Boundary

ns

7

Din Bit n Data Setup time from

STB rising

+(n-1) x

ns

n=1-8

8

Din Data Hold time from STB

rising

+(n-1) x

ns

(BCL)

Din

Dout

STB

70%

30%

70%

30%

70%

30%

70%

30%

NOTE:

CLOCKin