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MT9126AS Datasheet(PDF) 9 Page - Mitel Networks Corporation |
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MT9126AS Datasheet(HTML) 9 Page - Mitel Networks Corporation |
9 / 22 page Preliminary Information MT9126 8-41 Figure 4 - SSI 8-Bit Companded PCM Relative Timing Figure 5 - SSI 16-Bit Linear PCM Relative Timing ADPCM i/o BCLK ENB1 ENB2/F0od PCMi/o1 ADPCM i/o SEL = 0 SEL = 1 32 kb/s 24 kb/s 16 kb/s SEL for 16 kb/s only B1 B2 PCMi/o2 1234 B1 B2 12 3x B1 B2 12 B3 B4 12 12 12 1212 12 12 765 3 4 210 B3 B4 1234 1 23x 1234 B3 B4 123 x 1234 12 3x B1 B2 B3 B4 765 3 4 210 765 3 4 210 765 3 4 210 X = undetermined logic level output; don’t care input Two frame delay from data input to data output Outputs high impedance outside of channel strobe boundaries ENB1 ENB2/F0od EN1 ADPCM i/o ADPCMi/o B 1 1234 1234 1234 1234 123x 123x 123x 123x 12 SEL = 1 SEL = 1 SEL = 0 BCLK ... SEL for 16 kb/s only (2.048 MHz only) PCMi/o1 PCMi/o2 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 B1 B2 S = 3 bits sign extension µ−Law is 13 bit 2’s complement data (bits 0 -12) A-Law is 12 bit 2’s complement data (shifted left once and utilizing bits 1 - 12, bit 0 not defined) 32 kb/s 24 kb/s 16 kb/s B3 B4 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 Notes: B 2 B 3 B 4 12 12 12 B 1 12 B 2 B 3 B 4 12 12 12 B1 B2 B3 B4 1234 1234 123x 123x B3 B4 B 1 12 B 2 B 3 B 4 12 12 12 X = undetermined logic level output; don’t care input Two frame delay from data input to data output Outputs high impedance outside of channel strobe boundaries |
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