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MT90823 Datasheet(PDF) 9 Page - Mitel Networks Corporation |
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MT90823 Datasheet(HTML) 9 Page - Mitel Networks Corporation |
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9 / 34 page  CMOS MT90823 9 mode requires a CLK of 8.192 MHz and allows a maximum non-blocking capacity of 1,024 x 1,024 channels. 8.192 Mb/s Serial Links (DR0=0, DR1=1) When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 128 64 kb/s channels. This mode requires a CLK of 16.384 MHz and allows a maximum non-blocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship between different serial data rates and the master clock frequencies. Table 1- Switching Configuration Input Frame Offset Selection Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. F0i). This feature is useful in compensating for variable path delays caused by serial backplanes of variable lengths, which may be implemented in large centralized and distributed switching systems. Each input stream can have its own delay offset value by programming the frame input offset (FOR) registers. Possible adjustment can range up to +4 master clock (CLK) periods forward with resolution of 1/2 clock period. The output frame offset cannot be offset or adjusted. See Figure 4, Table 11 and Table 12 for delay offset programming. Serial Input Frame Alignment Evaluation The MT90823 provides the frame evaluation (FE) input to determine different data input delays with respect to the frame pulse F0i. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the evaluation starts when the SFE bit in the IMS register is changed from low to high. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high. This signals that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before starting a new measurement cycle. In ST-BUS mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the ST-BUS frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame pulse. See Table 10 and Figure 3 for the description of the frame alignment register. This feature is not available when the WFP Frame Alignment mode is enabled (i.e., when the WFPS pin is connected to VDD). Memory Block Programming The MT90823 provides users with the capability of initializing the entire connection memory block in two frames. Bits 11 to 15 of every connection memory location will be programmed with the pattern stored in bits 5 to 9 of the IMS register. The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. The other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero. Loopback Control The loopback control (LPBK) bit of each connection memory location allows the ST-BUS output data to be looped backed internally to the ST-BUS input for diagnostic purposes. If the LPBK bit is high, the associated ST-BUS output channel data is internally looped back to the ST-BUS input channel (i.e., data from STo n channel m routes to the STi n channel m internally); if the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero. Delay Through the MT90823 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice application, select variable throughput Serial Interface Data Rate Master Clock Required (MHz) Matrix Channel Capacity 2 Mb/s 4.096 512 x 512 4 Mb/s 8.192 1,024 x 1,024 8 Mb/s 16.384 2,048 x 2,048 |
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