Electronic Components Datasheet Search |
|
NCP5901BMNTBG Datasheet(PDF) 7 Page - ON Semiconductor |
|
NCP5901BMNTBG Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 9 page NCP5901B http://onsemi.com 7 APPLICATIONS INFORMATION The NCP5901B gate driver is a single phase MOSFET driver designed for driving N−channel MOSFETs in a synchronous buck converter topology. The NCP5901B is designed to work with ON Semiconductor’s NCP6131 multi−phase controller. This gate driver is optimized for desktop applications. Undervoltage Lockout The DRVH and DRVL are held low until VCC reaches 4.5 V during startup. The PWM signals will control the gate status when VCC threshold is exceeded. If VCC decreases to 250 mV below the threshold, the output gate will be forced low until input voltage VCC rises above the startup threshold. Power−On Reset Power−On Reset feature is used to protect a gate driver avoid abnormal status driving the startup condition. When the initial soft−start voltage is higher than 2.75 V, the gate driver will monitor the switching node SW pin. If SW pin high than 2.25 V, bottom gate will be force to high for discharge the output capacitor. The fault mode will be latch and EN pin will force to be low, unless the driver is recycle. When input voltage is higher than 4.5 V, and EN goes high, the gate driver will normal operation, top gate driver DRVH and bottom gate driver will follow the PWM signal decode to a status. Bi−directional EN Signal Fault modes such as Power−On Reset and Undervoltage Lockout will de−assert the EN pin, which will pull down the DRON pin of controller as well. Thus the controller will be shut down consequently. PWM Input and Zero Cross Detect (ZCD) The PWM input, along with EN and ZCD, control the state of DRVH and DRVL. When PWM is set high, DRVH will be set high after the adaptive non−overlap delay. When PWM is set low, DRVL will be set high after the adaptive non−overlap delay. When the PWM is set to the mid state, DRVH will be set low, and after the adaptive non−overlap delay, DRVL will be set high. DRVL remains high during the ZCD blanking time. When the timer is expired, the SW pin will be monitored for zero cross detection. After the detection, the DRVL will be set low. Adaptive Nonoverlap The nonoverlap dead time control is used to avoid the shoot through damage the power MOSFETs. When the PWM signal pull high, DRVL will go low after a propagation delay, the controller will monitors the switching node (SWN) pin voltage and the gate voltage of the MOSFET to know the status of the MOSFET. When the low side MOSFET status is off an internal timer will delay turn on of the high–side MOSFET. When the PWM pull low, gate DRVH will go low after the propagation delay (tpd DRVH). The time to turn off the high side MOSFET is depending on the total gate charge of the high−side MOSFET. A timer will be triggered once the high side MOSFET is turn off to delay the turn on the low−side MOSFET. Low−Side Driver Timeout In normal operation, the DRVH signal tracks the PWM signal and turns off the Q1 high−side switch with a few 10 ns delay (tpdlDRVH) following the falling edge of the input signal. When Q1is turned off, DRVL is allowed to go high, Q2 turns on, and the SW node voltage collapses to zero. But in a fault condition such as a high−side Q1 switch drain−source short circuit, the SW node cannot fall to zero, even when DRVH goes low. This driver has a timer circuit to address this scenario. Every time the PWM goes low, a DRVL on−time delay timer is triggered. If the SW node voltage does not trigger a low−side turn−on, the DRVL on−time delay circuit does it instead, when it times out with tSW(TO) delay. If Q1 is still turned on, that is, its drain is shorted to the source, Q2 turns on and creates a direct short circuit across the VDCIN voltage rail. The crowbar action causes the fuse in the VDCIN current path to open. The opening of the fuse saves the load (CPU) from potential damage that the high−side switch short circuit could have caused. Layout Guidelines Layout for DC−DC converter is very important. The bootstrap and VCC bypass capacitors should be placed as close as to the driver IC. Connect GND pin to local ground plane. The ground plane can provide a good return path for gate drives and reduce the ground noise. The thermal slug should be tied to the ground plane for good heat dissipation. To minimize the ground loop for low side MOSFET, the driver GND pin should be close to the low−side MOSFET source pin. The gate drive trace should be routed to minimize the length, the minimum width is 20 mils. Gate Driver Power Loss Calculation The gate driver power loss consists of the gate drive loss and quiescent power loss. The equation below can be used to calculate the power dissipation of the gate driver. Where QGMFis the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET. PDRV + [ f SW 2 n nMF QGMF ) nSF QGSF ) ICC] VCC Also shown is the standby dissipation factor (ICC ⋅ VCC) of the driver. |
Similar Part No. - NCP5901BMNTBG |
|
Similar Description - NCP5901BMNTBG |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |