NCP1256

www.onsemi.com

4

S

R

Q

Q

65/100

kHz clock

Jitter

mod.

Vcc

Drv

Vcc and logic

management

Vdd

power

on reset

LEB1

vdd

/ 3

4 ms

SS

Power on

reset

GND

CS

FB

1−us time

constant

Frequency

foldback

Vlatch1

Vfold

S

R

Q

Q

Clamp

Up counter

4

double

hiccup

RST

Event

gone?

peak current

freeze

VFB < 0.75 V ? setpoint = 250 mV

UVLO

BO

VBO1

VBO2

BO

VOVP

20 us

Ip

flag = 1 if over current

−−> start timer −−> auto rec.

invert

vdd

OPPGM

IOPPLL

Vlatch2

RFB

Validated

during off time

(option)

ICSO

Pre−short

Latched OCP

(option)

UVLO?

checked at

PON only

latched OCP opt.

Iopp3

VFB < VfoldF Iopp3 = 0

VFB > VoppF Iopp3 = I1

I2=0

I1=I2

VFB

RdBO

DZBO

I1

I2

BO

reset

= 1 if timer

completed

OCP timer completed

Auto−recovery dble hiccup

OVP on BO

OVP on CS

Logic

mngt

1−us time

constant

Figure 4. Internal Block Diagram

Auto−recovery

for E version

no clamp

for E version

Table 3. MAXIMUM RATINGS TABLE

Symbol

Rating

Value

Unit

−0.3 to 28

V

Maximum voltage on low power pins CS, FB and BO

−0.3 to 10

V

Maximum voltage on DRV pin

V

Thermal Resistance Junction−to−Air

360

°C/W

Maximum Junction Temperature

150

°C

Storage Temperature Range

−60 to +150

°C

HBM

Human Body Model ESD Capability per JEDEC JESD22−A114F

4

kV

MM

Machine Model ESD Capability per JEDEC JESD22−A115C

200

V

CDM

Charged−Device Model ESD Capability per JEDEC JESD22−C101E

750

V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.