3-28

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

controls the three states of CV (pin 22) under all modes of operation. When HIGH, enables

CV and when LOW, puts it in high impedance condition. It also controls the three states of

LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input.

2

MS0

with MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and

2).

3

C12i

Clock 12.355 MHz input (TTL compatible) - Master clock input at 12.355 MHz

±100ppm for

DPLL #1.

4

MS1

with MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and

2)

5

F0i

Frame pulse input (TTL compatible) - This is the frame pulse input (pulled internally to

MHz) clock.

6

F0b

Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending

on the minor mode selected for the DPLL #2, it provides the 8 kHz frame pulse output or acts

7

MS2

with MS3 (pin 17) selects the minor mode of operation for the DPLL #2. (Refer to Table 3.)

8

C16i

Clock 16.388 MHz input (TTL compatible) - Master clock input at 16.388 MHz

±32 ppm for

DPLL #2.

Enable 4.096 MHz clock (TTL compatible input) - This active high input (pulled internally

condition.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

24

23

22

21

20

19

18

17

ENVC

MS0

C12i

MS1

F0i

F0b

MS2

C16i

ENC4o

C8Kb

C4o

VSS

VDD

RST

CV

CVb

Yo

Bi

Ai

MS3

ENC2o

C2o

C2o

C4b