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MT8841AN Datasheet(PDF) 8 Page - Mitel Networks Corporation |
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MT8841AN Datasheet(HTML) 8 Page - Mitel Networks Corporation |
8 / 10 page MT8841 5-18 † AC Electrical Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing. *Notes: 1. dBm=decibels above or below a reference power of 1mW into 600 Ω. 2. Using unity gain test circuit shown in Figure 6. 3. Mark and Space frequencies have the same amplitude. 4. Band limited random noise (200-3200Hz). 5. Referenced to the minimum input detection level. 6. FSK input data at 1200 ±12 baud. 7. OSC1 at 3.579545 MHz ±0.2%. 8. 10k to VSS, 50pF to VSS. 9. 10k to VDD, 50pF to VSS. 10. Function of signal condition. 11. The device will stop functioning within this time, but more time may be required to reach IDDQ. 12. For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations. Figure 7 - DATA and DCLK Output Timing Figure 8 - DR Output Timing AC Electrical Characteristics† - Timing Characteristics Sym Min Typ‡ Max Units Notes* 1 PWDN OSC1 Power-up time tPU 35 50 ms 2 Power-down time tPD 100 1000 µs 11 3 CD Input FSK to CD low delay tIAL 25 ms 4 Input FSK to CD high delay tIAH 8ms 5 Hysteresis 8 ms 6 DATA Rate 1188 1200 1212 bps 6,12 7 Input FSK to DATA delay tIDD 15 ms 8 DATA DCLK Rise time tR 200 ns 8 9 Fall time tF 200 ns 8 10 DATA to DCLK delay tDCD 6 416 µs 6, 7, 10 11 DCLK to DATA delay tCDD 6 416 µs 6, 7, 10 12 DCLK Frequency 1200 1202.8 1205 Hz 7 13 High time tCH 415 416 417 µs 7 14 Low time tCL 415 416 417 µs 7 15 DCLK DR DCLK to DR delay tCRD 415 416 417 µs 7 16 DR Rise time tRR 10 µs 9 17 Fall time tFF 200 ns 9 18 Low time tRL 415 416 417 µs 7 DATA DCLK tR tDCD tCDD tR tF tCL tCH tF tFF tRR tRL DR |
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