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NCV78713MW0G Datasheet(PDF) 11 Page - ON Semiconductor |
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NCV78713MW0G Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 31 page NCV78713 www.onsemi.com 11 Table 6. ELECTRICAL CHARACTERISTICS (continued) (All Min and Max parameters are guaranteed over full junction temperature (TJP) range (−40°C; 150°C), unless otherwise specified) Characteristic Unit Max Typ Min Condition Symbol 3 V DIGITAL INPUTS (TEST, TEST1, TEST2) High-Level Input Voltage VIN3HI 2.3 − − V Low-Level Input Voltage VIN3LO − − 0.8 V Pull Resistance RPD3 Pull-Down Resistance − − 60 k W SPI INTERFACE CSB Setup Time tCSS 0.5 − − ms CSB Hold Time tCSH 0.25 − − ms SCLK Low Time tWL 0.5 − − ms SCLK High Time tWH 0.5 − − ms Data-In (DIN) Setup Time, Valid Data before Rising Edge of CLK tSU 0.25 − − ms Data-In (DIN) Hold Time, Hold Data after Rising Edge of CLK tH 0.275 − − ms Output (DOUT) Disable Time (Note 23) tDIS 0.08 − 0.32 ms Output (DOUT) Valid (Note 23) tV1→0 − − 0.32 ms Output (DOUT) Valid (Note 24) tV0→1 − − 0.32 + t(RC) ms Output (DOUT) Hold Time tHO 0.01 − − ms CSB High Time tCS 1 − − ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 23. SDO low-side switch activation time. 24. Time depends on the SDO load and pull-up resistor. Figure 5. SPI Communication Timing DIN15 DOUT15 DOUT14 DOUT13 DOUT1 DOUT0 DIN14 DIN13 DIN1 DIN0 HI−Z DIN CSB DOUT SCLK VIH VIL Initial State of SCLK after CSB Falling Edge is Don’t Care, It Can be Low or High HI−Z VIH VIL VIH VIL VIH VIL tCS tCSH tDIS tWL tWH tHO tV tH tSU tCSS |
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