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NOIL1SN3000A Datasheet(PDF) 9 Page - ON Semiconductor |
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NOIL1SN3000A Datasheet(HTML) 9 Page - ON Semiconductor |
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9 / 57 page  NOIL1SN3000A http://onsemi.com 9 Figure 7. Column Multiplexing Scheme 6T Pixel Architecture The pixel architecture shown in Figure 8 features the global shutter combined with a high sensitivity and good parasitic light sensitivity (PLS). This pixel architecture is designed in an 8 mm x 8 mm pixel pitch and designed with a large fill factor to meet the electro-optical specifications as shown in Table 2 on page 3. Figure 8. Pixel Schematic reset sample Vmem 2.5 - 3.3V precharge Row sel. Figure 9 displays the electro-optical response of the LUPA3000 6T pixels at VDD = 2.5 V. Figure 9. Electro−optical Response of LUPA3000 Pixel Analog Front End Programmable Gain Amplifiers(PGA) LUPA3000 includes analog PGA (before each of the 64 ADCs) to maximize sensor array signal levels to the ADC dynamic range. Six gain settings are available through the SPI register interface to allow 1x, 1.5x, 2x, 2.25x, 3x, or 4x gain. The entire AFE signal processing and ADC concept for the LUPA3000 chip is shown in Figure 10. The analog signal processing frontend circuits provide programmable gain level. They also convert the single ended pixel voltage from each column (as referenced to the user programmable black or dark reference level) to a unipolar differential signal for the PGA stages. This is followed by a conversion to a bipolar differential signal to maximize the ADC dynamic range and noise immunity. |
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