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SM1350 Datasheet(PDF) 8 Page - Nippon Precision Circuits Inc |
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SM1350 Datasheet(HTML) 8 Page - Nippon Precision Circuits Inc |
8 / 21 page SM1350 series NIPPON PRECISION CIRCUITS—8 S0 to S3 chattering prevention function In binary select mode, S0 to S3 are sampled in sync with the 15.26 Hz clock during level-hold melody output. The chatter prevention function compares the data sampled 65.5 ms after a data transition on S0 to S3 with the data sampled 65.5 ms before the data transition. If the 2 data samples are the same, then the data transition is considered invalid. However, if they are the not the same indicating a true transition has occurred, melody output stops and only restarts again after 2 consecutive identical melody select data samples occur. Note that except for the “Select change retrigger [No]” master slice option and binary select mode with level hold output, the S0 to S3 chattering prevention circuit is disabled. Initialization When power on and ICN goes LOW, all pins and internal states are initialized to the states shown below. ICN initialization has priority over all other inputs. s Output pins • SP, SPN Open • MSB, MSBN VDD •CT VSS • BUSYN VDD s Serial melody counter Reset to first melody (S0 to S3 all 1) s Oscillator circuit Stopped Note: Refer to the "TIMING DIAGRAMS" section to confirm melody timing specifics. Figure 3. S0 to S3 chattering prevention timing 15.26Hz S0 to S3 #N #M #S 65.5 ms 65.5 ms 65.5 ms 65.5 ms 65.5 ms 65.5 ms #N #N #M #S Melody Output |
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