NCL30086

www.onsemi.com

5

Table 3. MAXIMUM RATINGS TABLE(S)

Symbol

Rating

Value

Unit

−0.3 to 30

Internally limited

V

mA

Maximum driver pin voltage, DRV pin, continuous voltage

Maximum current for DRV pin

−300, +500

V

mA

−0.3, 5.5 (Notes 2 and 5)

−2, +5

V

mA

Thermal Resistance Junction−to−Air

180

°C/W

Maximum Junction Temperature

150

°C

Operating Temperature Range

−40 to +125

°C

Storage Temperature Range

−60 to +150

°C

ESD Capability, HBM model (Note 3)

3.5

kV

ESD Capability, MM model (Note 3)

250

V

ESD Capability, CDM model (Note 3)

2

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V Zener diode. More positive and negative voltages can

be applied if the pin current stays within the −2 mA / 5 mA range.

3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,

Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.

4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds

±100 mA.

Description

Test Condition

Symbol

Min

Typ

Max

Unit

STARTUP AND SUPPLY CIRCUITS

Supply Voltage

Startup Threshold

Minimum Operating Voltage

Internal logic reset

16.0

8.2

8

4

18.0

8.8

−

5

20.0

9.4

−

6

V

25.5

26.8

28.5

V

−

−

5

20

−

−

ms

Startup current

−

13

30

mA

Startup current in fault mode

58

75

mA

Supply Current

Device Disabled/Fault

Device Enabled/No output load on DRV pin

Device Switching

0.8

–

−

1.0

2.6

3.0

1.2

4.0

4.5

mA

CURRENT SENSE

Maximum Internal current limit

0.95

1.00

1.05

V

240

300

360

ns

Propagation delay from current detection to gate

off−state

−

100

150

ns

6. Guaranteed by Design

NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after

an OTP situation.

SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.