NCD9830

http://onsemi.com

11

CIRCUIT INFORMATION

OPERATION

The NCD9830 is a low power successive approximation

ADC with a built in 8 channel multiplexer and 8 bit

resolution. The 8 bit resolution assures high noise immunity

and fast digitization that makes this device suitable for

medium to high speed applications. The device internal

circuitry operates at speed higher than the conversion time

of the device because of the binary algorithm used. The

algorithm is based on approximating the input signal by

comparing with successive analog signal generated from the

built in DAC.

The device can be operated at supply voltages of 2.7 V and

5 V. The liberty of supply voltage variation must be used

with appropriate reference voltage selection. The NCD9830

internal DAC can be configured with an externally (50 mV

−5 V) supplied or an internally internally generated

reference voltage of 2.5 V. However, to avail full dynamic

range an external reference of 5 V must be used while

operating the device at 5 V supply voltage. The internal 2.5

V reference voltage is sufficient for full dynamic range

while operating the device at 2.7 V.

The value of each output bit is evaluated on the basis of

output of the comparator. The converter requires

N conversion periods to give N bit digital output of the input

analog signal. The SAR register stores the digital equivalent

bits of the input analog signal and can be read by the master

device are

i.

Digital to Analog Converter

ii.

Comparator

iii.

Digital Logic

Digital to Analog Converter

A charge scaling DAC is used due to its compatibility with

the switch capacitor circuits. The DAC operation consists of

two phases called acquisition phase and the conversion

phase. The acquisition phase is analogous to sample and

hold circuit while the conversion phase is the process of

conversion of the internal digital word in to an analog

output.

Acquisition phase: The top plates of all the capacitors on

the array are connected to the ground and the bottom plates

are connected to the applied voltage Vin. Thus there is

a charge proportional to input voltage on the capacitor array.

After acquisition the top and bottom plates are disconnected

from their respective connections.

Figure 16. The Acquisition Phase of a Typical ADC

C

2C

4C

8C

128C

Vin

Conversion Phase: The conversion phase is administered

by a two phase non overlapping clock with phases

respectively.

During

grounded i.e the top plates of all the capacitors are now Vin

times higher than the ground. As the conversion process

starts the digital control sets all the bits zero except the MSB

in the SAR register. During the

with MSB is connected to VREF while others are connected

to ground. In this way the DAC generates analog voltage of

magnitude VREF/2. The analog output of DAC is compared

with the input analog signal. The digital control logic sets the

MSB to 1 if comparator output is high and 0 otherwise. Thus

the first step of SAR algorithm decides whether the input

signal is greater or less than VREF/2. The approximation

process is then run again with the MSB in its proven value

and the next lower bit is set to 1. This gives a general

direction path and the remaining approximations will

converge the output in this direction.

Figure 17. The Conversion Phase of a Typical ADC

C

2C

4C

8C

128C

VREF

Vin

f2

f1

f2

f1 f2

f1 f2 f1

Comparator

A switch capacitor comparator is used to alleviate the

effects of input offset voltage. The issue of charge injection

is controlled by using fully differential topology.