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NR8576BB Datasheet(PDF) 9 Page - Nippon Precision Circuits Inc |
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NR8576BB Datasheet(HTML) 9 Page - Nippon Precision Circuits Inc |
9 / 10 page NR8576 Series NIPPON PRECISION CIRCUITS—9 Data Read Data is output when WR is LOW and CE is HIGH. Time and calendar data is loaded into shift registers on the first rising edge of the clock CLK, and the sec- onds’ digit LSB is output on DATA. The data is then loaded and shifted in the sequence second, minute, hour, week, day, and month on the rising edge of CLK, and output on DATA. The output data is valid after 52 rising edges of the clock; data input after 52 cycles does not alter the first 52 bits of valid data. WR CE CLK DATA S1 second year FDT S40 S20 S10 S8 S4 S2 y80 y40 y20 y10 y8 1 2 3 52 53 54 54+n OUTPUT MODE NON CHANGE OUTPUT DATA Within the 52 cycles of valid data, data already input can be output if there is a falling edge of CE after the corresponding number of cycles. For example, the data comprising the second-to-week is output is CE goes LOW after 28 clock cycles. For continuous data reads, a wait time (tRCV) is required before the next data cycle if CE has gone LOW. Note that if an update operation (a 1 s carry) occurs during a data read, an error of −1 s in the read data is generated. The data read time should be completed after tCE ≤ 0.9 s. |
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