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KAI-0373-AAA-CP-BA Datasheet(PDF) 11 Page - ON Semiconductor |
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KAI-0373-AAA-CP-BA Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 21 page KAI−0373 www.onsemi.com 11 OPERATION Absolute Maximum Ratings Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the condition is exceeded, the device will be degraded and may be damaged. Table 9. ABSOLUTE MAXIMUM RATINGS Rating Description Min. Max. Unit Notes Temperature (@ 10% ±5% RH) Operation to Specification 25 40 °C Operation Without Damage −25 55 °C Storage −25 70 °C Voltage (Between Pins) SUB−WELL 0 50 V 1, 3 VRD, VDD, and VSS−WELL 0 25 V 2 All Clocks − WELL − 17 V 2 fV1 − fV2 − 17 V 2 fH1 − fH2 − 17 V 2 fH1, fH2 − fV2 − 17 V 2 fH2 − OG − 17 V 2 All Clocks − LTSH − 17 V 2 VLG, OG − WELL − 17 V 2 All Gates – LTSH − 17 V 2 Current Output Bias Current (IDD) − 10 mA Capacitance Output Load Capacitance (CLOAD) − 10 pF Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Under normal operating conditions the substrate voltage should be above +7 V, but may be pulsed to 40 V for electronic shuttering. 2. Care must be taken in handling so as not to create static discharge which may permanently damage the device. 3. Refer to Application Note Using Interline CCD Image Sensors s in High Intensity Visible Lighting Conditions. DC Bias Operating Conditions Table 10. DC BIAS OPERATING CONDITIONS Description Symbol Min. Nom. Max. Unit Notes Output Gate OG 1.5 2 2.5 V Reset Drain VRD 10 10.5 11 V Output Amplifier Return VSS 0.4 0.5 0.6 V Output Amplifier Load Gate VLG 1.7 2 2.5 V Output Amplifier Supply VDD 14.5 15 15.5 V Well WELL − 0 − V Lightshield LTSH − 0 − V Substrate SUB 7 VAB 25 V 1, 4 Output Bias Current IOUT 3 5 7 mA 2 ESD Bias ESD − −10 − V 3 1. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The substrate is clocked in electronic shutter mode operation. A shutter pulse with voltage less than 50 V for less than 100 ms is allowed. See AC Clock Level Conditions and AC Timing Requirements. Well and substrate biases should be established before other gate and diode potentials are applied. 2. A 1.8 k W resistor between VOUT and ground is recommended to obtain IOUT = 5 mA. VOUT must not be shorted to ground. 3. Pins 11 and 13 are biased to –10 V. The ESD bias must be at least 1 V more negative than fH1 and fH2 during sensor operation AND during camera power turn on. 4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. |
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