LE25CB643TT-BH

No.A2255-10/17

2. Status Register

The Status Register can perform detection state of a device and setup of protection. The register consists of 8 bits.

The Status Register's contents are shown in Table2.

Table 2 : Status Register

Bit

Name

Logic

Function

Default at Power up

0

Ready state

Bit0

RDY

1

Busy state (Write operation progress)

0

0

Write prohibition state

Bit1

WEN

1

Write possible state

0

0

Bit2

BP0

1

Non-volatile information

0

Bit3

BP1

1

The block protect information

Reference Status Registers BP0 and BP1

Non-volatile Information

Bit4

X

0

Reserve Bit

0

Bit5

X

0

Reserve Bit

0

Bit6

X

0

Reserve Bit

0

0

Status Register Write enable state

Bit7

SRWP

1

Status Register Write disable state

Non-volatile Information

2-1. Status Register Read (RDSR)

Status Register Read can read the Status Register’s contents, moreover it can read also during the write operation.

Figure5 shows timing waveform of a Status Register Read.

Status Register command consists of only the 1st bus, If OP-code (05h) dose writes in, synchronizing with falling edge

of SCK, the Status Register's contents will be outputted from SRWP (Bit7).

If the data is outputted until RDY (Bit0), and also SCK input continues still more, it returns to SRWP and data output is

continued. Data is outputted from the falling edge clock of the 1st bus cycle Bit0.

Status Register Read can be read always (also in case of inside of write cycle).

Figure 5: Read Status Register Timing Diagram

CS

SCK

05h

(0000101)

0

8CLK

Mode3

Mode0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SI

SO

7

6

5

4

3

2

1

0

7

Status Register Out

High Impedance