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NCP5209 Datasheet(PDF) 1 Page - ON Semiconductor |
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NCP5209 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 20 page © Semiconductor Components Industries, LLC, 2004 June, 2004 − Rev. 1 1 Publication Order Number: NCP5209/D NCP5209 4−In−1 PWM Buck and Tri−Linear Power Controller The NCP5209 4−In−1 PWM Buck and Tri−Linear Power Controller is a complete ACPI compliant power solution for MCH and DDR memory. This IC combines the high efficiency of a PWM controller for the VDDQ supply with the simplicity of linear regulator for the VTT termination voltage as well as the MCH core supply voltage. This IC contains a synchronous PWM buck controller for driving two external N−Ch FETs to form the DDR memory supply voltage (VDDQ). The DDR memory termination regulator (VTT) is designed to track at the half of reference voltage while sourcing and sinking current. The two linear regulator controllers driving two external N−Ch FETs are cascaded to produce the MCH core voltage (VMCH). Protective features include, soft−start circuitry, undervoltage monitoring of 5VDUAL, 5VATX and 12VATX, and thermal shutdown. The device is housed in a thermal enhanced space−saving QFN−20 package. Features • Synchronous PWM Buck Controller for VDDQ • Integrated Power FETs in VTT Regulator Source/Sink up to 2.0 A • Two Linear Regulator Drivers for VMCH • All External Power MOSFETs are N−Channel • Adjustable VDDQ and VMCH by External Dividers • VTT Tracks at Half of Reference Voltage or can be Adjusted Externally • Fixed Switching Frequency of 250 kHz for DDQ Regulator in Normal Mode • Doubled Switching Frequency of 500 kHz for DDQ Regulator in Standby Mode to Optimize Inductor Current Ripple and Efficiency • Soft−Start Protection for all Regulators • Undervoltage Monitoring of Supply Voltages • Overcurrent Protection for DDQ and VTT Regulators • Fully Complies with ACPI Power Sequencing Specifications • Short Circuit Protection Prevents Damage to Power Supply Due to Reverse DIMM Insertion • Thermal Shutdown • 5x6 QFN−20 Package Applications • DDR I and DDR II Memory and MCH Power Supply PIN CONNECTIONS ORDERING INFORMATION http://onsemi.com MARKING DIAGRAM COMP_DDQ SS SW_DDQ FBDDQ PGND BOOT VTT 5VDUAL VDDQ AGND FBVTT DDQ_REF FB1P5 BG_DDQ TG_DDQ OCDDQ BUF_Cut DRV_2P4 FB2P4 DRV_1P5 QFN−20 MN SUFFIX CASE 505AB 1 20 NCP5209 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week NCP5209 AWLYYWW 1 Device Package Shipping† NCP5209MNR2 6x5 mm QFN−20 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. NOTE: Pin 21 is the thermal pad on the bottom of the device. |
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