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NB3U1548CDR2G Datasheet(PDF) 2 Page - ON Semiconductor |
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NB3U1548CDR2G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 11 page NB3U1548C www.onsemi.com 2 Figure 2. Pin Configuration (Top View) OE VDD GND Q4 CLK_IN Q1 Q2 Q3 1 2 3 4 8 7 6 5 Table 1. PIN DESCRIPTIONS Number Name Type Description 1 CLK_IN Input Pulldown Single−ended clock input. LVCMOS interface levels. 2 Q1 Output Single−ended clock output. LVCMOS interface levels. 3 Q2 Output Single−ended clock output. LVCMOS interface levels. 4 Q3 Output Single−ended clock output. LVCMOS interface levels. 5 Q4 Output Single−ended clock output. LVCMOS interface levels. 6 GND Power Power supply ground. 7 VDD Power Power supply pin. 8 OE Input Pullup Output enable pin. See Table 3. LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance VDD = 3.465 V 14 pF VDD = 2.375 V 13 pF VDD = 1.95 V 13 pF VDD = 1.6 V 12 pF RPULLUP Input Pullup Resistor 51 k W RPULLDOWN Input Pulldown Resistor 51 k W ROUT Output Impedance VDD = 3.3 V ± 5% 9 W VDD = 2.5 V ± 5% 10 W VDD = 1.8 V ± 0.15 V 12 W VDD = 1.5 ± 0.1 V 15 W Function Table Table 3. OE CONFIGURATION TABLE Input Operation OE 0 Q[4:1] disabled (high−impedance) 1 (default) Q[4:1] enabled NOTE: OE is an asynchronous control. |
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