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NB3N3010BMNG Datasheet(PDF) 2 Page - ON Semiconductor |
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NB3N3010BMNG Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 9 page NB3N3010B http://onsemi.com 2 Figure 2. Pinout SOIC−8 / DFN8 (Top View) CLKA 1 2 3 4 8 7 6 5 ENABLEn S0 REF GND VDD CLKB CFILT NB3N3010B Table 1. PIN DESCRIPTION Pin Symbol I/O Description 1 ENABLEn LVTTL/ LVCMOS Input Low active Output Enable; Defaults HIGH when left open; Internal pull−up resistor to VDD. 2 S0 LVTTL/ LVCMOS Input Frequency Select Input. See input frequency select Table 2 for details. Defaults HIGH when left open. Internal pull−up resistor to VDD. 3 REF Input Reference Clock input 4 GND Power Supply Negative Supply Voltage; Ground 0 V. This pin provides GND return path to the VDD supply. 5 CFILT Analog Connection for external filter capacitor for internal +1.8 V regulator; see Figure 4. 6 CLKA LVCMOS Output Clock output, copy A (12.288 MHz) 7 CLKB LVCMOS Output Clock output, copy B (12.288 MHz) 8 VDD Power Supply Positive Supply Voltage, +3.3 V $5% |
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