LP62E16512-T_15 datasheet(11/14 Pages) AMICC

Part #	LP62E16512-T

Description	512K X 16 BIT LOW VOLTAGE CMOS SRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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11 / 14 page

LP62E16512-T Series

(August, 2004, Version 1.1)

10

AMIC Technology, Corp.

Timing Waveforms (continued)

Write Cycle 3

(Byte Enable Controlled)

tWC

tAW

Address

CS1

tWR3

tCW1 , tCW2

tBW2

tAS1

DATA IN

DATA OUT

WE

HB, LB

tWP

tDW

tDH

tOW

tWHZ4

CS2

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP, tBW) of a low

1

CS , WE and ( HB and , or LB ) or a high CS2.

3. tWR is measured from the earliest of

1

CS

or WE or ( HB and , or LB ) going high or CS2 going Low to the end of the

Write cycle.

4. OE level is high or low.

5. Transition is measured

±200mV from steady state. This parameter is sampled and not 100% tested.

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LP62E16512-T Datasheet(PDF) 11 Page - AMIC Technology

LP62E16512-T Datasheet(HTML) 11 Page - AMIC Technology

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