A67P16181/A67P06361 Series

(June, 2008, Version 1.0)

8

AMIC Technology, Corp.

Truth Table (Notes 5 - 7)

Operation

Address

Used

CE

CE2

CE2

ZZ

ADV/

LD

BWx

OE

CEN

CLK

I/O

Notes

Deselected Cycle,

Power-down

None

H

X

X

L

L

X

X

X

L

L

→H

High-Z

Deselected Cycle,

Power-down

None

X

H

X

L

L

X

X

X

L

L

→H

High-Z

Deselected Cycle,

Power-down

None

X

X

L

L

L

X

X

X

L

L

→H

High-Z

Continue Deselect

Cycle

None

X

X

X

L

H

X

X

X

L

L

→H

High-Z

1

READ Cycle

(Begin Burst)

External

L

L

H

L

L

H

X

L

L

L

→H

Q

READ Cycle

(Continue Burst)

Next

X

X

X

L

H

X

X

L

L

L

→H

Q

1,7

NOP/Dummy READ

(Begin Burst)

External

L

L

H

L

L

H

X

H

L

L

→H

High-Z

2

Dummy READ

(Continue Burst)

Next

X

X

X

L

H

X

X

H

L

L

→H

High-Z

1,2,7

WRITE Cycle

(Begin Burst)

External

L

L

H

L

L

L

L

X

L

L

→H

D

3

WRITE Cycle

(Continue Burst)

Next

X

X

X

L

H

X

L

X

L

L

→H

D

1,3,7

NOP/WRITE Abort

(Begin Burst)

None

L

L

H

L

L

L

H

X

L

L

→H

High-Z

2,3

WRITE Abort

(Continue Burst)

Next

X

X

X

L

H

X

H

X

L

L

→H

High-Z

1,2,3,7

IGNORE Clock Edge

(Stall)

Current

X

X

X

L

X

X

X

X

H

L

→H

-

4

SLEEP Mode

None

X

X

X

H

X

X

X

X

X

X

High-Z

Notes:

1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or

WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is

executed first.

2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE

Abort means a WRITE command is given, but no operation is performed.

3.

OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the

output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their

requirements.

4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs

during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock

Edge cycle.

7. The address counter is incremented for all Continue Burst cycles.