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KAI-11002-CBA-CD-B1 Datasheet(PDF) 8 Page - ON Semiconductor |
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KAI-11002-CBA-CD-B1 Datasheet(HTML) 8 Page - ON Semiconductor |
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8 / 33 page  KAI−11002 www.onsemi.com 8 Output Figure 7. Output Architecture VDD VOUT Floating Diffusion HCCD Charge Transfer Source Follower #1 H1B H1S H2B H2S H1BIN OG R RD 31 k W Source Follower #2 Source Follower #3 Charge packets contained in the horizontal register are dumped pixel by pixel onto the floating diffusion (FD) output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential charge is determined by the expression DVFD =Q/ DCFD. A three-stage source-follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of microvolts per electron ( mV/e−). After the signal has been sampled off chip, the reset clock (R) removes the charge from the floating diffusion and resets its potential to the reset drain voltage (RD). |
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