KAF−16801

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10

TIMING

Table 10. REQUIREMENTS AND CHARACTERISTICS

Description

Symbol

Minimum

Nominal

Maximum

Units

Notes

fH1, fH2 Clock Frequency

−

8

15

MHz

1, 2, 3

fV1, fV2 Clock Frequency

−

25

25

MHz

1, 2, 3

Pixel Period (1 Count)

67

125

−

ns

fH1, fH2 Set-up Time

0.5

1

−

ms

fV1, fV2 Clock Pulse Width

40

40

−

ms

2

fV1, fV2 Clock Pulse Overlap

20

20

−

ms

Reset Clock Width

10

20

−

ns

4

Readout Time

1,398

2,390

−

ms

5

Integration Time

−

−

−

6

Line Time

338.7

580

−

ms

7

1. 50% duty cycle values.

2. CTE may degrade above the nominal frequency.

3. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Cross-over of register clocks should be between 40−60%

of amplitude.

4.

fR should be clocked continuously.

6. Integration time is user specified. Longer integration times will degrade noise performance.

Frame Timing

Figure 7. Frame Timing Diagram

1 Frame = 4128 Lines

4128

4127

2

1

Line

fV1

fV2

fH1

fH2