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A43E26161 Datasheet(PDF) 4 Page - AMIC Technology |
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A43E26161 Datasheet(HTML) 4 Page - AMIC Technology |
4 / 45 page A43E26161 (October, 2009, Version 1.8) 3 AMIC Technology, Corp. Pin Descriptions Symbol Name Description CLK System Clock Active on the positive going edge to sample all inputs. CS Chip Select Disables or Enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one clock + tss prior to new command. Disable input buffers for power down in standby. A0~A11 Address Row / Column addresses are multiplexed on the same pins. Row address : RA0~RA11, Column address: CA0~CA7 BS0, BS1 Bank Select Address Selects bank to be activated during row address latch time. Selects band for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write Enable Enables write operation and Row precharge. L(U)DQM Data Input/Output Mask Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ0-15 Data Input/Output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Supply/Ground Power Supply: +1.7V ~ 2.0V/Ground VDDQ/VSSQ Data Output Power/Ground Provide isolated Power/Ground to DQs for improved noise immunity. NC/RFU No Connection |
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