NB3L8543S

www.onsemi.com

2

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Q0

Q0

Q1

Q1

Q2

Q2

GND

Q3

Q3

GND

CLK_EN

CLK_SEL

CLK

PCLK

PCLK

OE

GND

CLK

Figure 2. Pinout Diagram (Top View)

Table 1. PIN DESCRIPTION

Number

Name

I/O

Open

Default

Description

1, 9, 13

GND

Power

Negative (Ground) Power Supply pins must be externally connected

to power supply to guarantee proper operation.

2

CLK_EN

NC

Pullup

Synchronized Clock Enable when HIGH. When LOW, outputs are

disabled (Qx HIGH, Qx LOW). See Figure 3.

3

CLK_SEL

NC

Pulldown

Clock Input Select (HIGH selects PCLK/PCLK, LOW selects CLK/

CLK input

4

CLK

Input

Pulldown

True Standard Clock Input. Float open when unused.

5

CLK

Input

Pullup

Invert Standard Clock Inputs. Float open when unused.

6

PCLK

Input

Pulldown

True Peripheral Clock Input. Float open when unused.

7

PCLK

Input

Pullup

Invert Peripheral Clock Inputs. Float open when unused.

8

OE

NC

Pullup

Output Enable Control. When HIGH, the outputs are active and en-

abled. When LOW, the outputs are high impedance disabled.

10 ,18

VDD

Power

Positive Power Supply pin must be externally connected to power

supply to guarantee proper operation.

11, 14, 16,

19

Q[3:0]

Output

Invert LVDS Outputs

12, 15, 17,

20

Q[3:0]

Output

True LVDS Outputs