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LM5037 Datasheet(PDF) 3 Page - Texas Instruments |
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LM5037 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 40 page  1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RAMP UVLO COMP FB RT2 AGND RT1/SYNC CS VIN REF VCC OUTA OUTB PGND SS RES LM5037 www.ti.com SNVS578D – NOVEMBER 2008 – REVISED MAY 2015 5 Pin Configuration and Functions PW PACKAGE 16 PIN TSSOP (TOP VIEW) Pin Functions PIN I/O(1) DESCRIPTION NAME NO. AGND 6 — Analog ground. Connect directly to power ground COMP 3 I/O Input to the pulse width modulator. Output of the error amplifier and input to the PWM comparator. Current sense input. If the CS pin exceeds 250 mV the output pulse terminates, entering cycle-by- CS 8 I cycle current limit. An internal switch holds the CS pin low for a period of 65 ns after either output switches high to blank leading edge transients. Feedback. Connected to inverting input of the error amplifier. An internal 1.25-V reference is FB 4 I connected to the non-inverting input of the error amplifier. In isolated applications using an external error amplifier, this pin should be connected to the analog ground pin (AGND). OUTA 13 Output driver. Alternating gate-drive output of the pulse width modulator. These pins are capable of O 1.2-A peak source and sink current. OUTB 12 PGND 11 — Power ground. Connect directly to the analog ground pin (AGND). Pulse width modulator ramp. Modulation ramp for the PWM comparator. This ramp can be a RAMP 1 I representative of the primary current (current mode) or proportional to input voltage (feed-forward voltage mode). This pin is reset to ground at the conclusion of every cycle by an internal FET. Output of a 5V reference. Locally decouple with a capacitor with a value of 0.1-µF or greater. REF 15 O Maximum output current is 10 mA (typ). Restart timer. If cycle-by-cycle current limit is reached during any cycle, the device sources 18 µA of current to the external RES pin capacitor. If the RES capacitor voltage reaches 2.0 V, the soft-start RES 9 I capacitor is discharged and then released with a pull-up current of 1 µA. After the first output pulse (when SS = 1 V), the SS pin charging current increases to the normal level of 100 µA. Oscillator dead-time control. The resistance connected between this pin (RT1/SYNC) and the AGND RT1/SYNC 7 I pin sets the oscillator maximum on-time. The sum of this maximum on-time and the forced dead-time (set by the RT2 pin) sets the oscillator period. Oscillator dead-time control. The resistance connected between this pin (RT2) and the AGND pin RT2 5 I sets the forced dead-time between switching periods of the alternating outputs. Soft-start. An external capacitor and an internal 100-µA current source set the soft-start ramp. The SS 10 I SS current source is reduced to 1 µA following a restart event (RES pin high). Line undervoltage lockout. An external voltage divider from the power source sets the shutdown and standby comparator threshold levels. When the UVLO pin exceeds the 0.45-V shutdown threshold, UVLO 2 I the VCC pin and REF pin regulators are enabled. When the UVLO pin exceeds the 1.25-V standby threshold, the SS pin is released and the device enters the active mode. Output of the high voltage start-up regulator. The VCC pin voltage is regulated to 7.7 V. If an auxiliary winding raises the voltage on this pin above the regulation set point, the internal start-up regulator VCC 14 I/O shuts down thus reducing the power dissipation of the device. Locally decouple the VCC pin with a capacitor with a value of 0.47 µF or greater. Input voltage source. Input to the VCC start-up regulator. Operating input range is 13 V to 100 V. For VIN 16 I power sources outside of this range, the LM5037device can be biased directly at the VCC pin by an external regulator. (1) I = Input, O = Output, G = Ground Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM5037 |
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