MC100LVEP05

http://onsemi.com

2

Figure 1. 8-Lead Pinout (Top View) and Logic

Diagram

1

2

3

45

6

7

8

Q

Q

Table 1. PIN DESCRIPTION

Pin

Function

D0*, D1*, D0**, D1**

ECL Data Inputs

Q, Q

ECL Data Outputs

Positive Supply

Negative Supply

EP

Exposed pad must be connected to a

sufficient thermal conduit. Electrically

connect to the most negative supply

or leave floating open.

* Pins will default LOW when left open.

Table 2. TRUTH TABLE

D0

D1

D0

D1

Q

Q

L

L

H

H

L

H

L

H

H

H

L

L

H

L

H

L

L

L

L

H

H

H

H

L

Table 3. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

75 k

W

Internal Input Pullup Resistor

37.5 k

W

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 4 kV

> 200 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

TSSOP-8

DFN8

Pb Pkg

Level 1

Level 1

Pb-Free Pkg

Level 3

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

Transistor Count

167 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.