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KAI-2020-AAA-CF-AE Datasheet(PDF) 8 Page - ON Semiconductor |
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KAI-2020-AAA-CF-AE Datasheet(HTML) 8 Page - ON Semiconductor |
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8 / 37 page  KAI−2020 www.onsemi.com 8 Output Figure 7. Output Architecture VDD VOUT Floating Diffusion HCCD Charge Transfer Source Follower #1 Source Follower #2 Source Follower #3 H2B OG R RD H1S H1B H2S H2B H1S VDD VSS Charge packets contained in the horizontal register are dumped pixel by pixel onto the floating diffusion (FD) output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential charge is determined by the expression DVFD = DQ/CFD. A three-stage source-follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of microvolts per electron ( mV/e−). After the signal has been sampled off chip, the reset clock (R) removes the charge from the floating diffusion and resets its potential to the reset drain voltage (RD). When the image sensor is operated in the binned or summed interlaced modes there will be more than 20,000 e− in the output signal. The image sensor is designed with a30 mV/e charge to voltage conversion on the output. This means a full signal of 20,000 electrons will produce a 600 mV change on the output amplifier. The output amplifier was designed to handle an output swing of 600 mV at a pixel rate of 40 MHz. If 40,000 electron charge packets are generated in the binned or summed interlaced modes then the output amplifier output will have to swing 1,200 mV. The output amplifier does not have enough bandwidth (slew rate) to handle 1,200 mV at 40 MHz. Hence, the pixel rate will have to be reduced to 20 MHz if the full dynamic range of 40,000 electrons is desired. The charge handling capacity of the output amplifier is also set by the reset clock voltage levels. The reset clock driver circuit is very simple if an amplitude of 5 V is used. But the 5 V amplitude restricts the output amplifier charge capacity to 20,000 electrons. If the full dynamic range of 40,000 electrons is desired then the reset clock amplitude will have to be increased to 7 V. If you only want a maximum signal of 20,000 electrons in binned or summed interlaced modes, then a 40 MHz pixel rate with a 5 V reset clock may be used. The output of the amplifier will be unpredictable above 20,000 electrons so be sure to set the maximum input signal level of your analog to digital converter to the equivalent of 20,000 electrons (600 mV). |
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