KAF-4301 Image Sensor

www.truesenseimaging.com

Revision 2.1 PS-0038Pg7

H22

Sub

Vdd2

Vout2

Vss

Vdd1

Vout1

R

Vrd

Vog

H21

FD2

FD1

Vlg

H2

H1

Figure 2: Output Structure

Output Structure

The final gate of the horizontal register is split into two sections, φH21 and φH22 as shown in Figure 2. The split gate

structure allows the user to select either of the two output amplifiers. To use the high dynamic range single-stage

output (Vout1), φH22 is tied to a negative voltage to block charge transfer, and φH21 is tied to φH2 to transfer

charge. To use the high sensitivity two-stage output (Vout2), φH21 is tied to a negative voltage and φH22 is tied to

φH2. The charge packets are then dumped onto the appropriate floating diffusion output node whose potential varies

linearly with the quantity of charge in each packet. The amount of potential change is determined by the simple

expression Vfd = Q/Cfd. The translation from electrons to voltages is called the output sensitivity or charge-to-voltage

conversion. After the output has been sensed off-chip, the reset clock (φR) removes the charge from the floating

diffusion via the reset drain (VRD). This, in turn, returns the floating diffusion potential to the reference level

determined by the reset drain voltage.

An image is acquired when incident light, in the form of photons, falls on the array of pixels in the vertical CCD register

and creates electron-hole pairs (or simply electrons) within the silicon substrate. This charge is collected locally by the

formation of potential wells created at each pixel site by induced voltages on the vertical register clock lines

(φV1, φV2). These same clock lines are used to implement the transport mechanism as well. The amount of charge

collected at each pixel is linearly dependent on light level and exposure time and non-linearly dependent on

wavelength until the potential well capacity is exceeded. At this point charge will 'bloom' into vertically adjacent pixels.

Integrated charge is transported to the output in a two-step process. Rows of charge are first shifted line by line into

the horizontal CCD. 'Lines' of charge are then shifted to the output pixel by pixel. Referring to the timing diagrams in

Figure 8, integration of charge is performed with φV1 and φV2 held low. Transfer to the horizontal CCD begins when

φV1 is brought high causing charge from the φV1 and φV2 gates to combine under the φV1 gate. φV1 and φV2 now

are reversed in polarity causing the charge packets to 'spill' forward under the φV2 gate of the next pixel. The rising

edge of φV2 also transfers the first line of charge into the horizontal CCD. A second phase transition places the charge

packets under the φV1 electrode of the next pixel. The sequence completes when φV1 is brought low. Clocking of the

vertical register in this way is known as accumulation mode clocking. Next, the horizontal CCD transfersout the first

line of charge using traditional complementary clocking (using φH1 and φH2 pins) as shown. The falling edge of φH2

forces a charge packet over the output gate (OG) onto one of the output nodes (floating diffusion) that controls the

output amplifier. The cycle repeats until all lines are read.