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TPS65287 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS65287 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 75 page TPS65400-Q1 www.ti.com SLVSCQ2 – JULY 2015 7.6 System Characteristics The following specification table entries are specified by the design (component values provided in the typical application circuit are used). These parameters are not specified by production testing. Minimum and Max values apply over the full operating ambient temperature range (–40°C ≤ TJ ≤ 125°C), over the VIN range = 5 to 12 V, and IOUT range unless otherwise specified. L = 3.3 µH, DCR = 10.4 m Ω, VOUT = 1.2 V, 1% FB resistor. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VLINEREG Line regulation 0.1 %/V VLOADREG Load regulation 0.1 %/A tr VOUT step duration (tr) For 50-mV step 30 µs ts VOUT step settling time (ts) For 50-mV step 30 µs VOVUV VOUT step overshoot/undershoot For 50-mV step 6 mV Vin = 5 V, Vo = 1.2 V, Iout = 4 A, 77% ƒsw = 500 kHz Efficiency (SW1 and SW2) Vin = 12 V, Vo = 1.2 V Iout = 4 A, 76% ƒsw = 500 kHz Vin = 5 V, Vo = 1.2 V, Iout = 2 A, 77% ƒsw= 500 kHz Efficiency (SW3 and SW4) Vin = 12 V, Vo = 1.2 V Iout = 2 A, 74% ƒsw = 500 kHz Average ((1)) current sharing IOUTmatch accuracy (SW1 and SW2, SW3 and Iload = IOUTmax 20% SW4) Peak current ((2)) sharing accuracy IPKmatch Iload = IOUTmax 20% (SW1 and SW2, SW3 and SW4) Timing accuracy for delays and tacc –10% 10% restarts Time after RSTn or CE is released treset_delay Default value 1 ms for power sequence to begin Minimum delay after reset is treset_delay_max released for power sequence to treset_delay set to 0 ms 1.1 ms 0 begin (1) Average current sharing accuracy is highly dependent on the matching of the inductor and capacitor. (2) Peak current sharing accuracy refers to the max inductor current in each phase. 7.7 Operational Parameters Values recommended that ensure proper system behavior PARAMETER MIN TYP MAX UNIT CA Stabilization capacitor to be connected to VDDA 4.7 µF CD Stabilization capacitor to be connected to VDDD 3.3 µF CG Stabilization capacitor to be connected to VDDG 10 µF Vin1, Vin2, Vin3, Vin4 SW1 to SW4 input voltage 4.5 18 V Vout1, Vout2, Vout3, Vout4 SW1 to SW4 output voltage 0.6 90% of Vin V 7.8 Package Dissipation Ratings (1) PACKAGE RθJA (°C/W) TA = 25°C TA = 55°C TA = 85°C RGZ 29.8 4.5 W 3.14 W 1.77 W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS65400-Q1 |
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