SN74LS90

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3

FUNCTIONAL DESCRIPTION

The LS90, LS92, and LS93 are 4-bit ripple type Decade,

Divide-By-Twelve, and Binary Counters respectively. Each

device consists of four master/slave flip-flops which are

internally connected to provide a divide-by-two section and a

divide-by-five

(LS90),

divide-by-six

(LS92),

or

divide-by-eight (LS93) section. Each section has a separate

clock input which initiates state changes of the counter on the

HIGH-to-LOW clock transition. State changes of the Q

outputs do not occur simultaneously because of internal

ripple delays. Therefore, decoded output signals are subject

to decoding spikes and should not be used for clocks or

device.

provided on all counters which overrides and clocks and

resets (clears) all the flip-flops. A gated AND asynchronous

overrides the clocks and the MR inputs and sets the outputs

to nine (HLLH).

Since the output from the divide-by-two section is not

internally connected to the succeeding stages, the devices

may be operated in various counting modes.

LS90

receives the incoming count and a BCD count sequence

is produced.

C. Divide-By-Two and Divide-By-Five Counter — No

external interconnections are required. The first flip-flop is

used as a binary element for the divide-by-two function

output.

LS92

symmetrical divide-by-twelve square wave output.

B. Divide-By-Two and Divide-By-Six Counter —No external

interconnections are required. The first flip-flop is used as

output.

LS93

shown in the truth table.

B. 3-Bit Ripple Counter— The input count pulses are applied

Independent use of the first flip-flop is available if the reset

function coincides with reset of the 3-bit ripple-through

counter.