MT9V115W00STCK22EC1-750 datasheet(11/51 Pages) ONSEMI

Part #	MT9V115W00STCK22EC1-750

Description	Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor

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MT9V115 DS Rev. E Pub. 5/15 EN

11

©Semiconductor Components Industries, LLC, 2015.

MT9V115: 1/13-Inch VGA SOC Digital Image Sensor

Functional Description

Power-On Reset

The MT9V115 includes a power-on reset feature that initiates a reset upon power-up. A

soft reset is issued by writing commands through the two-wire serial interface.

Two types of reset are available:

• A soft reset is issued by writing commands (SYSCTL R0x001A[0] = 1)through the two-

wire serial interface register 0x1A bit[4:6] during normal operation.

•An internal power-on reset

The output states after hard reset are shown in Table 5 on page 11.

A soft reset sequence to the sensor has the same effect as the hard reset and can be acti-

vated by writing to a register through the two-wire serial interface. On-chip power-

onreset circuitry can generate an internal reset signal in case an external reset is not

provided. The RESET_BAR signal has an internal pull-up resistor and can be left floating.

Standby

The MT9V115 supports two different standby modes:

1. Hard standby mode

2. Soft standby mode

The hard standby mode is invoked by asserting the STANDBY pin. It then disables all of

the digital logic within the image sensor, and only supports being awoken by de-

asserting the STANDBY pin. The soft standby mode is enabled by a single register access,

which then disables the sensor core and most of the digital logic. However, the serial

interface is kept alive, which allows the image sensor to be awoken via a serial register

access.

All output signal status during standby are shown in Table 5.

Hard Standby Mode

The MT9V115 can enter hard standby mode by using external STANDBY signal, as

shown in Figure 3. The two-wire serial interface and IFP block shut down even when

EXTCLK is running during hard standby mode.

Table 5:

Status of Output Signals During Reset and Standby

Signal

Reset

Post-Reset

Standby

DOUT[7:0]

High-Z

PIXCLK

High-Z

LV

High-Z

FV

High-Z

CLK_N

High-Z

0

CLK_P

High-Z

0

DATA_N

High-Z

0

DATA_P

High-Z

0

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