3

Exposed

Thermal Pad

9

10

11

12

8

7

6

5

4

2

1

16

15

14

13

PVIN

PVIN

AVIN

SS/TR

SW

SW

SW

PG

TPS62150A-Q1, TPS62153A-Q1

www.ti.com

SLVSCC3 – MAY 2014

6 Device Comparison Table

PART NUMBER

OUTPUT VOLTAGE

PACKAGE MARKING

TPS62150AQ

adjustable

-40°C to 125°C

PA8IQ

TPS62153AQ

5V

-40°C to 125°C

PA8JQ

7 Pin Configuration and Functions

VQFN Package

16-Pin

Top View

Pin Functions

I/O

DESCRIPTION

NAME

NO.

SW

1,2,3

O

Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and

output capacitor.

PG

4

O

Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires

pull-up resistor)

FB

5

I

Voltage feedback pin. Connect resistive voltage divider to this pin.

AGND

6

Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

LOG

7

I

This pin is used for internal logic and must be connected to GND.

DEF

8

I

Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise

SS/TR

9

I

time. It can be used for tracking and sequencing.

AVIN

10

I

Supply voltage for control circuitry. Connect to same source as PVIN.

PVIN

11,12

I

Supply voltage for power stage. Connect to same source as AVIN.

EN

13

I

VOS

14

I

Output voltage sense pin and connection for the control loop circuitry.

PGND

15,16

Power Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

Exposed

Thermal Pad

achieve appropriate power dissipation and mechanical reliability.

(1)

For more information about connecting pins, see Detailed Description and Application and Implementation sections.

(2)

An internal pull-down resistor keeps logic level low, if pin is floating.

(3)

See Figure 37.

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