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MT9M114D00STCZK24BC1-200 Datasheet(PDF) 11 Page - ON Semiconductor |
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MT9M114D00STCZK24BC1-200 Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 66 page MT9M114 DS Rev. J Pub. 4/15 EN 11 ©Semiconductor Components Industries, LLC,2015. MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig- ital Image Sensor Power-Up and Power-Down Sequence Powering up and powering down the sensor requires voltages to be applied in a partic- ular order, as seen in Figure 4. The timing requirements are shown in Table 4. The sensor includes a power-on reset feature that initiates a reset upon power up of the sensor Figure 4: Power-Up and Power-Down Sequence Notes: 1. Under the condition of EXTCLK=24MHz and default settings with CONFIG=1. 2. The host should poll the Command register to determine when the device is initialized. Table 4: Power-Up and Power-Down Signal Timing Symbol Parameter Min Typ Max Unit t1 Delay from VDD_IO to VDD and VDD_PHY 0 – 50 ms t2 Delay from VDD_IO to VAA and VDD_PLL 0 – 50 ms t3 EXTCLK activation t2 – – ms t4 First serial command1, 2 –44.5 – ms t5 EXTCLK cutoff t6 – – ms t6 Delay from VAA and VDD_PLL to VDD_IO 0 – 50 ms t7 Delay from VDD and VDD_PHY toVDD_IO 0 – 50 ms VDD_IO EXTCLK SCLK SDATA t2 t1 t3 t4 t5 t6 t7 VDD, VDD_PHY VAA, VDD_PLL |
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