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MT9F002I12STCV-DP Datasheet(PDF) 11 Page - ON Semiconductor |
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MT9F002I12STCV-DP Datasheet(HTML) 11 Page - ON Semiconductor |
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11 / 93 page  MT9F002 DS Rev. H Pub. 6/15 EN 11 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Operating Modes 6. The parallel interface output pads can be left unconnected when the serial output interface is used. 7. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Check the MT9F002 demo headboard schematics for circuit recom- mendations. 8. TEST signals must be tied to DGND for normal sensor operation. 9. ON Semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 10. For serial HiSPi HiVCM mode, set register bit R0x306E[9] = 1 and VDD_TX = VDD_IO = 1.8V. Figure 6: Typical Configuration: Parallel Pixel Data Interface Notes: 1. All power supplies should be adequately decoupled. ON Semiconductor recommends having 1.0F and 0.1F decoupling capacitors for every power supply. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The GPI pins can be statically pulled HIGH or LOW and can be programmed to perform special func- tions (TRIGGER/VD, OE_BAR, SADDR, STANDBY) to be dynamically controlled. GPI pads can be left floating, when not used. 5. VPP, which is not shown in Figure 6, is left unconnected during normal operation. 6. The serial interface output pads can be left unconnected when the parallel output interface is used. 7. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Check the MT9F002 demo headboard schematics for circuit recom- mendations. 8. TEST signals must be tied to DGND for normal sensor operation. VAA_PIX VDD Master clock (2–64 MHz) SDATA SCLK RESET_BAR TEST FLASH FRAME_VALID SHUTTER DOUT [11:0] EXTCLK DGND AGND Digital ground Analog ground Digital core power1 To controller parallel port From Controller LINE_VALID PIXCLK VDD_IO GPI[3:0]4 Digital I/O power1 VDD_IO VDD_PLL VDD VAA VAA VAA_PIX Analog power1 VDD_PLL PLL power1 Analog power1 1.0 µF 0.1µF 0.1 µF 1.0 µF 0.1 µF 1.0 µF 0.1 µF 1.0 µF 0.1 µF 1.0 µF |
Similar Part No. - MT9F002I12STCV-DP |
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Similar Description - MT9F002I12STCV-DP |
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