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MT9D115EB3STC-CR Datasheet(PDF) 6 Page - ON Semiconductor |
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MT9D115EB3STC-CR Datasheet(HTML) 6 Page - ON Semiconductor |
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6 / 66 page  MT9D115: 1/5-Inch SOC Digital Image Sensor Functional Description MT9D115 DS Rev. E Pub. 4/15 EN 6 ©Semiconductor Components Industries, LLC,2015. Functional Description The ON Semiconductor MT9D115 is a 1/5-inch 2 Mp CMOS digital image sensor with an integrated advanced camera system. This camera system features a microcontroller (MCU), a sophisticated image flow processor (IFP), MIPI and parallel output ports (only one output port can be used at a time). The microcontroller manages all functions of the camera system and sets key operation parameters for the sensor core to optimize the quality of raw image data entering the IFP. The IFP will be responsible for processing and enhancing the image. The entire system-on-a-chip (SOC) has superior low-light performance that is particu- larly suitable for PC camera applications. The MT9D115 features ON Semiconductor’s breakthrough low-noise CMOS imaging technology that achieves near-CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The ON Semiconductor MT9D115 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 800x600 image size at 30 frames per second (fps), assuming a 24 MHz input clock. It outputs 8-bit data, using the parallel output port. Architecture Overview The MT9D115 combines a 2 Mp sensor core with an IFP to form a stand-alone solution for both image acquisition and processing. Both the sensor core and the IFP have internal registers that can be controlled by the user. In normal operation, an integrated microcontroller autonomously controls most aspects of operation. The processed image data is transmitted to the host system either through the parallel or MIPI interface. Figure 1 shows the major functional blocks of the MT9D115. Figure 1: MT9D115 Block Diagram Pixel Array Sensor C ore FIFO Im age F low Processor(IF P ) Stats Engine C olor Pipeline Parallel Output Interface M icrocontroller SR AM ROM POR Two- W ire Serial IF Internal R egister Bus System C ontrol M icrocontroller U nit (MCU) MIPI |
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