4 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D47.pm5 – Rev. 3/97

©1997, Micron Technology, Inc.

10

4 MEG x 4

EDO DRAM

TECHNOLOGY, INC.

NOTES

2. The minimum specifications are used only to indicate

cycle time at which proper operation over the full

temperature range (0˚C

3. An initial pause of 100

µs is required after power-up,

followed by eight RAS# refresh cycles (RAS#-ONLY

or CBR with WE# HIGH), before proper device

operation is ensured. The eight RAS# cycle wake-ups

requirement is exceeded.

4. NC pins are assumed to be left floating and are not

tested for leakage.

Specified values are obtained with minimum cycle

time and the outputs open.

6. Column address changed once each cycle.

7. Enables on-chip refresh and address counters.

measuring timing of input signals. Transition times

11. In addition to meeting the transition rate specifica-

12. Measured with a load equivalent to two TTL gates

(MIN), the cycle is an EARLY WRITE cycle and the

data output will remain an open circuit throughout

≥

and the data output will contain data read from the

selected cell. If neither of the above conditions is met,

the state of data-out is indeterminate. OE# held HIGH

and WE# taken LOW after CAS# goes LOW results in

WRITE cycle.

15. If CAS# is LOW at the falling edge of RAS#, Q will be

maintained from the previous cycle. To initiate a new

cycle and clear the data-out buffer, CAS# must be

16. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading edge

in LATE WRITE or READ-MODIFY-WRITE cycles.

17. If OE# is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not permis-

sible and should not be attempted. Additionally, WE#

must be pulsed during CAS# HIGH time in order to

place I/O buffers in High-Z.

18. LATE WRITE and READ-MODIFY-WRITE cycles

during WRITE cycle) in order to ensure that the

output buffers will be open during the WRITE cycle.

The DQs will provide the previously read data if

CAS# remains LOW and OE# is taken back LOW

going back LOW, the DQs will remain open.

achieves the open circuit condition and is not

rising edge of RAS# or CAS#, whichever occurs last.

(MAX) was specified as a reference point only. If

limit, then access time was controlled exclusively by

must always be met.

(MAX) was specified as a reference point only. If

limit, then access time was controlled exclusively by

be met.

cycle.

24. A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# is LOW and

OE# is HIGH.

or 64ms (4K refresh) to 128ms (both 2K and 4K

µs (128ms/

4,096 rows = 31.25

(128ms/2,048 rows = 62.5

µs).