MT58L1MY18D datasheet(6/34 Pages) MICRON

Part #	MT58L1MY18D

Description	16Mb SYNCBURST??SRAM

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Manufacturer	MICRON [Micron Technology]

Direct Link	http://www.micron.com

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6

16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT58L1MY18D_2.p65 – Rev 7/00

16Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, DCD SYNCBURST SRAM

ADVANCE

TQFP PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL

TYPE

DESCRIPTION

84

ADSP#

Input

Synchronous Address Status Processor: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent

upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-

down state is entered if CE2 is LOW or CE2# is HIGH.

85

ADSC#

Input

Synchronous Address Status Controller: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ or WRITE is performed using the new address if

CE# is LOW. ADSC# is also used to place the chip into power-down

state when CE# is HIGH.

31

MODE

Input

Mode: This input selects the burst sequence. A LOW on this pin

(LBO#)

selects “linear burst.” NC or HIGH on this pin selects “interleaved

burst.” Do not alter input state while device is operating. LBO# is

the JEDEC-standard term for MODE.

(a) 58, 59,

(a) 52, 53,

DQa

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with

62, 63, 68, 69, 56-59, 62, 63

Output DQa pins; Byte “b” is associated with DQb pins. For the x32 and

72, 73

x36 versions, Byte “a” is associated with DQa pins; Byte “b” is

(b) 8, 9, 12,

(b) 68, 69

DQb

associated with DQb pins; Byte “c” is associated with DQc pins;

13, 18, 19, 22, 72-75, 78, 79

Byte “d” is associated with DQd pins. Input data must meet setup

23

and hold times around the rising edge of CLK.

(c) 2, 3, 6-9,

DQc

12, 13

(d) 18, 19,

DQd

22-25, 28, 29

74

51

NC/DQPa

NC/

No Connect/Parity Data I/Os: On the x32 version, these pins are No

24

80

NC/DQPb

I/O

Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte

–

1

NC/DQPc

“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;

–

30

NC/DQPd

Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is

DQPd.

15, 41, 65,

VDD

Supply Power Supply: See DC Electrical Characteristics and Operating

91

Conditions for range.

4, 11, 20, 27,

VDDQ

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and

54, 61, 70, 77 54, 61, 70, 77

Operating Conditions for range.

5, 10, 17, 21,

VSS

Supply Ground: GND.

26, 40, 55, 60, 26, 40, 55, 60,

67, 71, 76, 90 67, 71, 76, 90

38, 39

DNU

–

Do Not Use: These signals may either be unconnected or wired to

GND to improve package heat dissipation.

1-3, 6, 7, 14

14, 16, 66

NC

–

No Connect: These signals are not internally connected and may be

16, 25, 28-30,

connected to ground to improve package heat dissipation.

51-53, 56, 57,

66, 75, 78, 79,

95, 96

NA

NF

–

No Function: These pins are internally connected to the die and

have the capacitance of an input pin. It is allowable to leave these

pins unconnected or driven by signals.

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