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MT4LC16M4A7DJ-6 Datasheet(PDF) 3 Page - Micron Technology |
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MT4LC16M4A7DJ-6 Datasheet(HTML) 3 Page - Micron Technology |
3 / 20 page 3 16 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D21_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM addressed via the address bits. First, the row address is latched by the RAS# signal, then the column address by CAS#. Both devices provide FAST-PAGE-MODE opera- tion, allowing for fast successive data operations (READ, WRITE, or READ-MODIFY-WRITE) within a given row. The MT4LC16M4A7 and MT4LC16M4T8 must be refreshed periodically in order to retain stored data. FAST PAGE MODE ACCESS Each location in the DRAM is uniquely addressable as mentioned in the General Description. The data for each location is accessed via the four I/O pins (DQ0- DQ3). The WE# signal must be activated to execute a WRITE operation; otherwise, a READ operation will be performed. The OE# signal must be activated to enable the DQ output drivers for a read access and can be deactivated to disable output data if necessary. FAST-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the FAST-PAGE-MODE opera- tion. DRAM REFRESH The supply voltage must be maintained at the speci- fied levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all 8,192 rows (A7) or all 4,096 rows (T8) in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC16M4A7 internally refreshes two rows for every CBR cycle, whereas the MT4LC16M4T8 refreshes one row for every CBR cycle. So with either device, executing 4,096 CBR cycles covers all rows. The CBR refresh will invoke the internal refresh counter for automatic RAS# address- ing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method only one row is refreshed at a time; so for the MT4LC16M4A7, 8,192 RAS#-ONLY REFRESH cycles must be executed every 64ms to cover all rows. Some compatibility issues may become apparent. JEDEC strongly recommends the use of CBR REFRESH for this device. An optional self refresh mode is also available on the “S” version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The “S” option allows for an extended refresh period of 128ms, or 31.25µs per row for a 4K refresh and 15.625µs per row for an 8K refresh, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM con- troller utilizes RAS#-ONLY or burst CBR refresh se- quence, all rows must be refreshed within the average internal refresh rate prior to the resumption of normal operation. STANDBY Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time. GENERAL DESCRIPTION (continued) |
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