4 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D47.pm5 – Rev. 3/97

©1997, Micron Technology, Inc.

1

4 MEG x 4

EDO DRAM

TECHNOLOGY, INC.

4 MEG x 4 EDO DRAM PART NUMBERS

PART NUMBER

Vcc

REFRESH

PACKAGE

REFRESH

MT4LC4M4E8DJ

3.3V

2K

SOJ

Standard

MT4LC4M4E8DJS

3.3V

2K

SOJ

Self

MT4LC4M4E8TG

3.3V

2K

TSOP

Standard

MT4LC4M4E8TGS

3.3V

2K

TSOP

Self

MT4LC4M4E9DJ

3.3V

4K

SOJ

Standard

MT4LC4M4E9DJS

3.3V

4K

SOJ

Self

MT4LC4M4E9TG

3.3V

4K

TSOP

Standard

MT4LC4M4E9TGS

3.3V

4K

TSOP

Self

MT4C4M4E8DJ

5V

2K

SOJ

Standard

MT4C4M4E8DJS

5V

2K

SOJ

Self

MT4C4M4E8TG

5V

2K

TSOP

Standard

MT4C4M4E8TGS

5V

2K

TSOP

Self

MT4C4M4E9DJ

5V

4K

SOJ

Standard

MT4C4M4E9DJS

5V

4K

SOJ

Self

MT4C4M4E9TG

5V

4K

TSOP

Standard

MT4C4M4E9TGS

5V

4K

TSOP

Self

MT4LC4M4E8, MT4C4M4E8

MT4LC4M4E9, MT4C4M4E9

DRAM

FEATURES

• Industry-standard x4 pinout, timing, functions and

packages

• State-of-the-art, high-performance, low-power CMOS

silicon-gate process

• Single power supply (+3.3V

±0.3V or +5V ±10%)

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-

BEFORE-RAS# (CBR)

• Optional Self Refresh (S) for low-power data retention

• 11 row, 11 column addresses (2K refresh) or

12 row, 10 column addresses (4K refresh)

• Extended Data-Out (EDO) PAGE MODE access cycle

• 5V-tolerant inputs and I/Os on 3.3V devices

OPTIONS

MARKING

• Voltages

3.3V

LC

5V

C

• Refresh Addressing

2,048 (i.e. 2K) Rows

E8

4,096 (i.e. 4K) Rows

E9

• Packages

Plastic SOJ (300 mil)

DJ

Plastic TSOP (300 mil)

TG

• Timing

50ns access

-5

60ns access

-6

• Refresh Rates

Standard Refresh

None

Self Refresh (128ms period)

S

• Part Number Example: MT4LC4M4E8DJ-6

Note:

The 4 Meg x 4 EDO DRAM base number differentiates the offerings in

two places - MT4LC4M4E8. The third field distinguishes the low voltage

distinguishes various options: E8 designates a 2K refresh and E9 designates a

4K refresh for EDO DRAMs.

PIN ASSIGNMENT (Top View)

24/26-Pin SOJ

(DA-2)

DQ1

DQ2

WE#

RAS#

*NC/A11

A10

A0

A1

A2

A3

1

2

3

4

5

6

8

9

10

11

12

13

26

25

24

23

22

21

19

18

17

16

15

14

DQ4

DQ3

CAS#

OE#

A9

A8

A7

A6

A5

A4

DQ1

DQ2

WE#

RAS#

*NC/A11

A10

A0

A1

A2

A3

1

2

3

4

5

6

8

9

10

11

12

13

26

25

24

23

22

21

19

18

17

16

15

14

DQ4

DQ3

CAS#

OE#

A9

A8

A7

A6

A5

A4

24/26-Pin TSOP

(DB-2)

* NC on 2K refresh and A11 on 4K refresh options.

GENERAL DESCRIPTION

The 4 Meg x 4 DRAM is a randomly accessed, solid-state

memory containing 16,777,216 bits organized in a x4 con-

figuration. RAS# is used to latch the row address (first 11

bits for 2K and first 12 bits for 4K). Once the page has been

opened by RAS#, CAS# is used to latch the column address

KEY TIMING PARAMETERS

SPEED

-5

84ns

50ns

20ns

25ns

13ns

8ns

-6

104ns

60ns

25ns

30ns

15ns

10ns

Note:

The “#” symbol indicates signal is active LOW.