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MT4LC4M4B1DJ-6 Datasheet(PDF) 1 Page - Micron Technology

Part # MT4LC4M4B1DJ-6
Description  DRAM
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT4LC4M4B1DJ-6 Datasheet(HTML) 1 Page - Micron Technology

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1
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 – Rev. 5/00
©2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
4 MEG x 4 FPM DRAM PART NUMBERS
REFRESH
PART NUMBER
VCC ADDRESSING PACKAGE REFRESH
MT4LC4M4B1DJ-6
3.3V
2K
SOJ
Standard
MT4LC4M4B1DJ-6 S 3.3V
2K
SOJ
Self
MT4LC4M4B1TG-6
3.3V
2K
TSOP
Standard
MT4LC4M4B1TG-6 S 3.3V
2K
TSOP
Self
MT4LC4M4A1DJ-6
3.3V
4K
SOJ
Standard
MT4LC4M4A1DJ-6 S 3.3V
4K
SOJ
Self
MT4LC4M4A1TG-6
3.3V
4K
TSOP
Standard
MT4C4M4A1TG-6S 3.3V
4K
TSOP
Self
MT4C4M4B1DJ-6
5V
2K
SOJ
Standard
MT4C4M4B1DJ-6 S
5V
2K
SOJ
Self
MT4C4M4B1TG-6
5V
2K
TSOP
Standard
MT4C4M4B1TG-6S
5V
2K
TSOP
Self
MT4C4M4A1DJ-6
5V
4K
SOJ
Standard
MT4C4M4A1DJ-6 S
5V
4K
SOJ
Self
MT4C4M4A1TG-6
5V
4K
TSOP
Standard
MT4C4M4A1TG-6S
5V
4K
TSOP
Self
MT4LC4M4B1, MT4C4M4B1
MT4LC4M4A1, MT4C4M4A1
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
DRAM
FEATURES
• Industry-standard x4 pinout, timing, functions,
and packages
• High-performance, low-power CMOS silicon-gate
process
• Single power supply (+3.3V ±0.3V or +5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
• Optional self refresh (S) for low-power data
retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• FAST-PAGE-MODE (FPM) access
• 5V tolerant inputs and I/Os on 3.3V devices
OPTIONS
MARKING
• Voltage
3.3V
LC
5V
C
• Refresh Addressing
2,048 (2K) rows
B1
4,096 (4K) rows
A1
• Packages
Plastic SOJ (300 mil)
DJ
Plastic TSOP (300 mil)
TG
• Timing
50ns access
-5
60ns access
-6
• Refresh Rates
Standard Refresh
None
Self Refresh (128ms period)
S *
NOTE: 1. The 4 Meg x 4 FPM DRAM base number differenti-
ates the offerings in one place—MT4LC4M4B1. The
fifth field distinguishes various options: B1
designates a 2K refresh and A1 designates a 4K
refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC4M4B1DJ
**NC on 2K refresh and A11 on 4K refresh options.
PIN ASSIGNMENT (Top View)
VCC
DQ0
DQ1
WE#
RAS#
**NC/A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
DQ3
DQ2
CAS#
OE#
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
DQ1
WE#
RAS#
**NC/A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
DQ3
DQ2
CAS#
OE#
A9
A8
A7
A6
A5
A4
VSS
24/26-Pin SOJ
24/26-Pin TSOP
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tPC
tAA
tCAC
tRP
-5
84ns
50ns
20ns
25ns
13ns
30ns
-6
110ns
60ns
35ns
30ns
15ns
40ns


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