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MT4LC4M4B1 Datasheet(PDF) 6 Page - Micron Technology

Part # MT4LC4M4B1
Description  DRAM
Download  20 Pages
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT4LC4M4B1 Datasheet(HTML) 6 Page - Micron Technology

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6
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 – Rev. 5/00
©2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN)
£ Vcc £ Vcc (MAX)]
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from column address
tAA
25
30
ns
Column-address hold time (referenced to RAS#)
tAR
38
45
ns
Column-address setup time
tASC
0
0
ns
Row-address setup time
tASR
0
0
ns
Column address to WE# delay time
tAWD
42
49
ns
18
Access time from CAS#
tCAC
13
15
ns
Column-address hold time
tCAH
8
10
ns
CAS# pulse width
tCAS
8
10,000
10
10,000
ns
CAS# LOW to “Don’t Care” during Self Refresh
tCHD
15
15
ns
CAS# hold time (CBR Refresh)
tCHR
8
10
ns
4
CAS# to output in Low-Z
tCLZ
0
0
ns
22
CAS# precharge time
tCP
8
10
ns
13
Access time from CAS# precharge
tCPA
28
35
ns
CAS# to RAS# precharge time
tCRP
5
5
ns
CAS# hold time
tCSH
38
45
ns
CAS# setup time (CBR Refresh)
tCSR
5
5
ns
4
CAS# to WE# delay time
tCWD
28
35
ns
18
WRITE command to CAS# lead time
tCWL
8
10
ns
Data-in hold time
tDH
8
10
ns
19
Data-in setup time
tDS
0
0
ns
19
Output disable
tOD
0
12
0
15
ns
22
Output enable
tOE
12
15
ns
20
OE# hold time from WE# during
tOEH
8
10
ns
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
tOFF
0
12
0
15
ns
17, 22
OE# setup prior to RAS# during HIDDEN REFRESH cycle
tORD
0
0
ns
FAST-PAGE-MODE READ or WRITE cycle time
tPC
20
25
ns
FAST-PAGE-MODE READ-WRITE cycle time
tPRWC
47
56
ns
Access time from RAS#
tRAC
50
60
ns
RAS# to column-address delay time
tRAD
9
12
ns
15
Row-address hold time
tRAH
9
10
ns
RAS# pulse width
tRAS
50
10,000
60
10,000
ns
RAS# pulse width (FAST PAGE MODE)
tRASP
50
125,000
60
125,000
ns
RAS# pulse width during Self Refresh
tRASS
100
100
µs
Random READ or WRITE cycle time
tRC
84
104
ns
RAS# to CAS# delay time
tRCD
11
14
ns
14
READ command hold time (referenced to CAS#)
tRCH
0
0
ns
16
READ command setup time
tRCS
0
0
ns
Refresh period (2,048 cycles)
tREF
32
32
ms
Refresh period (4,096 cycles)
tREF
64
64
ms


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