8

16 Meg x 4 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D21_2.p65 – Rev. 5/00

©2000, Micron Technology, Inc.

16 MEG x 4

FPM DRAM

NOTES

1.

2.

MHz.

3.

rates. Specified values are obtained with mini-

mum cycle time and the outputs open.

4.

Enables on-chip refresh and address counters.

5.

The minimum specifications are used only to

indicate cycle time at which proper operation

over the full temperature range is ensured.

6.

An initial pause of 100µs is required after power-

up, followed by eight RAS# refresh cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper

device operation is ensured. The eight RAS# cycle

refresh requirement is exceeded.

7.

8.

measuring timing of input signals. Transition

9.

In addition to meeting the transition rate

specification, all input signals must transit

monotonic manner.

the last valid READ cycle.

12. Measured with a load equivalent to two TTL

13. If CAS# is LOW at the falling edge of RAS#,

output data will be maintained from the previous

cycle. To initiate a new cycle and clear the data-

(MAX) limit, then access time was controlled

(MAX) limit, then access time was controlled

cycle.

achieves the open circuit condition and is not

cycle is an EARLY WRITE cycle and the data

output will remain an open circuit throughout

READ-MODIFY-WRITE cycles. Meeting these

limits allows for reading and disabling output

data and then applying input data. The values

shown were calculated for reference allowing

10ns for the external latching of read data and

application of write data. OE# held HIGH and

WE# taken LOW after CAS# goes LOW result in a

LATE WRITE cycle.

19. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

20. If OE# is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not

possible.

21. A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# = LOW and OE#

= HIGH.

22. RAS#-ONLY REFRESH requires that all 8,192 rows

of the MT4LC16M4A7 or all 4,096 rows of the

MT4LC16M4T8 be refreshed at least once every

64ms. CBR REFRESH for either device requires

that at least 4,096 cycles be completed every

64ms.

DQs will open regardless of the state of OE#. If

CAS# stays LOW while OE# is brought HIGH, the

DQs will open. If OE# is brought back LOW

(CAS# still LOW), the DQs will provide the

previously read data.

24. LATE WRITE and READ-MODIFY-WRITE cycles

during WRITE cycle) in order to ensure that the

output buffers will be open during the WRITE

cycle. If OE# is taken back LOW while CAS#

remains LOW, the DQs will remain open.

25. Column address changed once each cycle.

width

≤ 10ns, and the pulse width cannot be

≤

10ns, and the pulse width cannot be greater than

one third of the cycle rate.