5

4 Meg x 16 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D29_C.p65 – Rev. 2/01

©2001, Micron Technology, Inc.

4 MEG x 16

EDO DRAM

Figure 3

OE# Control of DQs

V

V

IH

IL

CAS#

V

V

IH

IL

RAS#

V

V

IH

IL

ADDR

ROW

COLUMN (A)

COLUMN (B)

V

V

IH

IL

OE#

V

V

IOH

IOL

OPEN

DQ

tOD

VALID DATA (B)

VALID DATA (A)

COLUMN (C)

VALID DATA (A)

tOE

VALID DATA (C)

COLUMN (D)

VALID DATA (D)

tOD

tOEHC

tOD

tOEP

tOES

The DQs go back to

The DQs remain High-Z

until the next CAS# cycle

The DQs remain High-Z

until the next CAS# cycle

Figure 4

WE# Control of DQs

V

V

IH

IL

CAS#

V

V

IH

IL

RAS#

V

V

IH

IL

ADDR

ROW

COLUMN (A)

DON’T CARE

UNDEFINED

V

V

IH

IL

WE#

V

V

IOH

IOL

OPEN

DQ

tWPZ

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

V

V

IH

IL

OE#

VALID DATA (B)

t

WHZ

WE# may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

t

WHZ

COLUMN (D)

VALID DATA (A)

COLUMN (B)

COLUMN (C)

INPUT DATA (C)