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MT4C1M16C3DJ-6 Datasheet(PDF) 9 Page - Micron Technology |
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MT4C1M16C3DJ-6 Datasheet(HTML) 9 Page - Micron Technology |
9 / 22 page 9 1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM NOTES 1. All voltages referenced to VSS. 2. This parameter is sampled. VCC = +3.3V or 5.0V; f = 1 MHz. 3. ICC is dependent on output loading. Specified values are obtained with minimum cycle time and the output open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ T A ≤ 70°C) for commercial and (-20°C ≤ T A ≤ 80°C) for extended “ET” is ensured. 6. An initial pause of 100µs is required after power- up, followed by eight RAS# refresh cycles (RAS#- ONLY or CBR), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh require- ment is exceeded. 7. AC characteristics assume tT = 5ns. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10. If CAS# = VIH, data output is High-Z. 11. If CAS# = VIL, data output may contain data from the last valid READ cycle. 12. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2V. 13. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the Q buffer, CAS# must be pulsed HIGH for tCP. 14. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. 15. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. 16. Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 18. tWCS, tRWD, tAWD, and tCWD are restrictive operating parameters in LATE WRITE and READ- MODIFY-WRITE cycles only. If tWCS ≥ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data out-put will remain an open circuit through- out the entire cycle. If tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of Q (at access time and until CAS# or OE# goes back to VIH) is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. During a READ cycle, if OE# is LOW then taken HIGH before CAS# goes HIGH, Q goes open. If OE# is tied permanently LOW, LATE WRITE and READ-MODIFY-WRITE operations are not permissible and should not be attempted. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 22. All other inputs at 0.2V or VCC - 0.2V. 23. Column address changed once each cycle. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after tOEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 25. The DQs open during READ cycles once tOD or tOFF occur. 26. The 3ns minimum is a parameter guaranteed by design. 27. The first CASx edge to transition LOW. 28. The last CASx edge to transition HIGH. 29. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 30. Last falling CASx edge to first rising CASx edge. 31. Last rising CASx edge to next cycle’s last rising CASx edge. |
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