10

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 – Rev. B; Pub 3/01

©2001, Micron Technology, Inc.

1 MEG x 16

FPM DRAM

NOTES (continued)

32. Last rising CASx edge to first falling CASx edge.

33. First DQs controlled by the first CASx to go LOW.

34. Last DQs controlled by the last CASx to go HIGH.

35. Each CASx must meet minimum pulse width.

36. Last CASx to go LOW.

37. All DQs controlled, regardless CASL# and CASH#.

38. If OE# is tied permanently LOW, LATE WRITE, or

READ-MODIFY-WRITE operations are not

permissible and should not be attempted.