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MT4C1M16E5 Datasheet(PDF) 2 Page - Micron Technology |
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MT4C1M16E5 Datasheet(HTML) 2 Page - Micron Technology |
2 / 24 page 2 1 Meg x 16 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D52_B.p65 – Rev. B; Pub. 3/01 ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM Figure 1 OE# Control of DQs V V IH IL CASL#/CASH# V V IH IL RAS# V V IH IL ADDR ROW COLUMN (A) COLUMN (B) DON’T CARE UNDEFINED V V IH IL OE# V V IOH IOL OPEN DQ tOD VALID DATA (B) VALID DATA (A) COLUMN (C) VALID DATA (A) tOE VALID DATA (C) COLUMN (D) VALID DATA (D) tOD tOEHC tOD tOEP tOES The DQs go back to Low-Z if tOES is met. The DQs remain High-Z until the next CAS# cycle if tOEHC is met. The DQs remain High-Z until the next CAS# cycle if tOEP is met. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READ-MODIFY- WRITE occurs when WE falls after CAS# (CASL# or CASH#) was taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READ- MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs will drive read data from the accessed location. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O. Pin direction is controlled by OE# and WE#. The 1 Meg x 16 DRAM must be refreshed periodi- cally in order to retain stored data. of the two signals results in a BYTE WRITE cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW se- lects an access cycle for the upper byte (DQ8-DQ15). Each bit is uniquely addressed through the 20 ad- dress bits during READ or WRITE cycles. These are entered 10 bits (A0-A9) at a time. RAS# is used to latch the first 10 bits and CAS#, the latter 10 bits. The CAS# function also determines whether the cycle will be a refresh cycle (RAS# ONLY) or an active cycle (READ, WRITE or READ-WRITE) once RAS# goes LOW. The CASL# and CASH# inputs internally generate a CAS# signal that functions like the single CAS# input on other DRAMs. The key difference is each CAS# input (CASL# and CASH#) controls its corresponding eight DQ inputs during WRITE accesses. CASL# controls DQ0-DQ7, and CASH# controls DQ8-DQ15. The two CAS# controls give the 1 Meg x 16 both BYTE READ and BYTE WRITE cycle capabilities. GENERAL DESCRIPTION (continued) |
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