MT46V8M16TG-8L datasheet(10/68 Pages) MICRON

Part #	MT46V8M16TG-8L

Description	DOUBLE DATA RATE DDR SDRAM

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Manufacturer	MICRON [Micron Technology]

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10

128Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01

128Mb: x4, x8, x16

DDR SDRAM

PRELIMINARY

Figure 1

Mode Register Definition

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a

block of columns equal to the burst length is effectively

selected. All accesses for that burst take place within this

block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1-Ai when the burst length is set to two, by

A2-Ai when the burst length is set to four and by A3-Ai

when the burst length is set to eight (where Ai is the

most significant column address bit for a given con-

TABLE 1

BURST DEFINITION

Burst

StartingColumn

Order of Accesses Within a Burst

Length

Address

Type=Sequential

Type=Interleaved

A0

2

0

0-1

1

1-0

A1 A0

0

0-1-2-3

4

0

1

1-2-3-0

1-0-3-2

1

0

2-3-0-1

1

3-0-1-2

3-2-1-0

A2 A1 A0

0

0-1-2-3-4-5-6-7

0

1

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

0

1

0

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

8

0

1

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

1

0

4-5-6-7-0-1-2-3

1

0

1

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

1

0

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

NOTE: 1. For a burst length of two, A1-Ai select the two-

data-element block; A0 selects the first access

within the block.

2. For a burst length of four, A2-Ai select the four-

data-element block; A0-A1 select the first access

within the block.

3. For a burst length of eight, A3-Ai select the eight-

data-element block; A0-A2 select the first access

within the block.

4. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

figuration). The remaining (least significant) address

bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to

both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the

starting column address, as shown in Table 1.

M3 = 0

Reserved

2

4

8

Reserved

M3 = 1

Reserved

2

4

8

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

0

1

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2

Reserved

2.5

Reserved

Burst Length

M0

0

1

0

1

0

1

0

1

Burst Length

CAS Latency BT

0*

A9

A7 A6 A5 A4 A3

A8

A2 A1 A0

Mode Register (Mx)

Address Bus

9

7

65

4

3

8

2

1

0

M1

0

1

0

1

M2

0

1

M3

M4

0

1

0

1

0

1

0

1

M5

0

1

0

1

M6

0

1

Valid

-

M6-M0

0

1

-

M8

0

-

M7

Operating Mode

A10

A11

BA0

BA1

10

11

12

13

* M13 and M12 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

0

-

M9

0

-

M10

0

-

M11

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